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公开(公告)号：US12056598B2
公开(公告)日：2024-08-06
申请号：US18046301
申请日：2022-10-13
发明人： Andrew S. Cassidy , Rathinakumar Appuswamy , John V. Arthur , Pallab Datta , Steven K. Esser , Myron D. Flickner , Jennifer Klamo , Dharmendra S. Modha , Hartmut Penner , Jun Sawada , Brian Taba
摘要： Hardware neural network processors, are provided. A neural core includes a weight memory, an activation memory, a vector-matrix multiplier, and a vector processor. The vector-matrix multiplier is adapted to receive a weight matrix from the weight memory, receive an activation vector from the activation memory, and compute a vector-matrix multiplication of the weight matrix and the activation vector. The vector processor is adapted to receive one or more input vector from one or more vector source and perform one or more vector functions on the one or more input vector to yield an output vector. In some embodiments a programmable controller is adapted to configure and operate the neural core.
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公开(公告)号：US11200496B2
公开(公告)日：2021-12-14
申请号：US15792155
申请日：2017-10-24
发明人： John V. Arthur , Pallab Datta , Steven K. Esser , Myron D. Flickner , Dharmendra S. Modha , Tapan K. Nayak
摘要： Hardware placement of neural networks is provided. In various embodiments, a network description is read. The network description describes a spiking neural network. The neural network is trained. An initial placement of the neural network on a plurality of cores is performed. The cores are located on a plurality of chips. Inter-chip communications are measured based on the initial placement. A final placement of the neural network on the plurality of cores is performed based on the inter-chip communications measurements and the initial placement. The final placement reduces inter-chip communication.
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公开(公告)号：US10679120B2
公开(公告)日：2020-06-09
申请号：US14537826
申请日：2014-11-10
发明人： Charles J. Alpert , Pallab Datta , Myron D. Flickner , Zhuo Li , Dharmendra S. Modha , Gi-Joon Nam
IPC分类号： G06N3/06 , G06N3/04 , G06F30/327 , G06N3/063 , G06F119/06
摘要： Embodiments of the present invention relate to providing power minimization in a multi-core neurosynaptic network. In one embodiment of the present invention, a method of and computer program product for power-driven synaptic network synthesis is provided. Power consumption of a neurosynaptic network is modeled as wire length. The neurosynaptic network comprises a plurality of neurosynaptic cores. An arrangement of the synaptic cores is determined by minimizing the wire length.
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4.发明申请公开(公告)号：US20200042856A1
公开(公告)日：2020-02-06
申请号：US16051034
申请日：2018-07-31
发明人： Pallab Datta , Andrew S. Cassidy , Myron D. Flickner , Hartmut Penner , Rathinakumar Appuswamy , Jun Sawada , John V. Arthur , Dharmendra S. Modha , Steven K. Esser , Brian Taba , Jennifer Klamo
摘要： Mapping of neural network layers to physical neural cores is provided. In various embodiments, a neural network description describing a plurality of neural network layers is read. Each of the plurality of neural network layers has an associated weight tensor, input tensor, and output tensor. A plurality of precedence relationships among the plurality of neural network layers is determined. The weight tensor, input tensor, and output tensor of each of the plurality of neural network layers are mapped onto an array of neural cores.
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公开(公告)号：US20200019836A1
公开(公告)日：2020-01-16
申请号：US16033926
申请日：2018-07-12
发明人： John V. Arthur , Andrew S. Cassidy , Myron D. Flickner , Pallab Datta , Hartmut Penner , Rathinakumar Appuswamy , Jun Sawada , Dharmendra S. Modha , Steven K. Esser , Brian Taba , Jennifer Klamo
摘要： Networks of distributed neural cores are provided with hierarchical parallelism. In various embodiments, a plurality of neural cores is provided. Each of the plurality of neural cores comprises a plurality of vector compute units configured to operate in parallel. Each of the plurality of neural cores is configured to compute in parallel output activations by applying its plurality of vector compute units to input activations. Each of the plurality of neural cores is assigned a subset of output activations of a layer of a neural network for computation. Upon receipt of a subset of input activations of the layer of the neural network, each of the plurality of neural cores computes a partial sum for each of its assigned output activations, and computes its assigned output activations from at least the computed partial sums.
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公开(公告)号：US20200012929A1
公开(公告)日：2020-01-09
申请号：US16028158
申请日：2018-07-05
发明人： Hartmut Penner , Dharmendra S. Modha , John V. Arthur , Andrew S. Cassidy , Rathinakumar Appuswamy , Pallab Datta , Steven K. Esser , Myron D. Flickner , Jennifer Klamo , Jun Sawada , Brian Taba
摘要： Instruction distribution in an array of neural network cores is provided. In various embodiments, a neural inference chip is initialized with core microcode. The chip comprises a plurality of neural cores. The core microcode is executable by the neural cores to execute a tensor operation of a neural network. The core microcode is distributed to the plurality of neural cores via an on-chip network. The core microcode is executed synchronously by the plurality of neural cores to compute a neural network layer.
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7.发明申请公开(公告)号：US20200005155A1
公开(公告)日：2020-01-02
申请号：US16024016
申请日：2018-06-29
发明人： Pallab Datta , Dharmendra S. Modha
摘要： Mapping of logical neural cores to physical neural cores is provided. In various embodiments, a neural network description describing a plurality of logical cores is read. A plurality of precedence relationships is determined among the plurality of logical cores. Based on the plurality of precedence relationships, a directed acyclic graph among the plurality of logical cores is generated. By breadth first search of the directed acyclic graph, a schedule is generated. The schedule maps each of the plurality of logical cores to one of a plurality of physical cores at one of a plurality of time slices. Execution of the schedule is simulated.
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公开(公告)号：US10338629B2
公开(公告)日：2019-07-02
申请号：US15273036
申请日：2016-09-22
发明人： Arnon Amir , Pallab Datta , Dharmendra Modha
摘要： Reduction in the number of neurons and axons in a neurosynaptic network while maintaining its functionality is provided. A neural network description describing a neural network is read. One or more functional unit of the neural network is identified. The one or more functional unit of the neural network is optimized. An optimized neural network description is written based on the optimized functional unit.
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公开(公告)号：US10317930B2
公开(公告)日：2019-06-11
申请号：US14871680
申请日：2015-09-30
发明人： Arnon Amir , Pallab Datta , Nimrod Megiddo , Dharmendra S. Modha
摘要： A computer-implemented method is provided for optimizing core utilization in a neurosynaptic network. The computer-implemented method comprises identifying one or more unused portions of a neurosynaptic network. Additionally, the computer-implemented method comprises, for each of the one or more unused portions of the neurosynaptic network, disconnecting the unused portion from the neurosynaptic network.
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公开(公告)号：US10282658B2
公开(公告)日：2019-05-07
申请号：US15239642
申请日：2016-08-17
发明人： Rodrigo Alvarez-Icaza Rivera , John V. Arthur , Andrew S. Cassidy , Pallab Datta , Paul A. Merolla , Dharmendra S. Modha
摘要： Embodiments of the invention relate to a neural network system for simulating neurons of a neural model. One embodiment comprises a memory device that maintains neuronal states for multiple neurons, a lookup table that maintains state transition information for multiple neuronal states, and a controller unit that manages the memory device. The controller unit updates a neuronal state for each neuron based on incoming spike events targeting said neuron and state transition information corresponding to said neuronal state.
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