-
1.发明授权公开(公告)号：US11205419B2
公开(公告)日：2021-12-21
申请号：US16115258
申请日：2018-08-28
IPC分类号： G10L15/16 , G06N3/02 , G10L15/06 , G06N3/06 , G10L25/30 , G06N3/04 , G10L25/24 , G10L25/12 , G06N3/08 , G10L15/02
摘要： Low energy deep-learning networks for generating auditory features such as mel frequency cepstral coefficients in audio processing pipelines are provided. In various embodiments, a first neural network is trained to output auditory features such as mel-frequency cepstral coefficients, linear predictive coding coefficients, perceptual linear predictive coefficients, spectral coefficients, filter bank coefficients, and/or spectro-temporal receptive fields based on input audio samples. A second neural network is trained to output a classification based on input auditory features such as mel-frequency cepstral coefficients. An input audio sample is provided to the first neural network. Auditory features such as mel-frequency cepstral coefficients are received from the first neural network. The auditory features such as mel-frequency cepstral coefficients are provided to the second neural network. A classification of the input audio sample is received from the second neural network.
-
公开(公告)号：US11049001B2
公开(公告)日：2021-06-29
申请号：US16049539
申请日：2018-07-30
发明人： Rodrigo Alvarez-Icaza Rivera , John V. Arthur , Andrew S. Cassidy , Bryan L. Jackson , Paul A. Merolla , Dharmendra S. Modha , Jun Sawada
IPC分类号： G06N3/063
摘要： The present invention provides a system comprising multiple core circuits. Each core circuit comprises multiple electronic axons for receiving event packets, multiple electronic neurons for generating event packets, and a fanout crossbar including multiple electronic synapse devices for interconnecting the neurons with the axons. The system further comprises a routing system for routing event packets between the core circuits. The routing system virtually connects each neuron with one or more programmable target axons for the neuron by routing each event packet generated by the neuron to the target axons. Each target axon for each neuron of each core circuit is an axon located on the same core circuit as, or a different core circuit than, the neuron.
-
公开(公告)号：US10929747B2
公开(公告)日：2021-02-23
申请号：US15950033
申请日：2018-04-10
发明人： Rodrigo Alvarez-Icaza , John V. Arthur , Andrew S. Cassidy , Bryan L. Jackson , Paul A. Merolla , Dharmendra S. Modha , Jun Sawada
摘要： One embodiment provides a system comprising a memory device for maintaining deterministic neural data relating to a digital neuron and a logic circuit for deterministic neural computation and stochastic neural computation. Deterministic neural computation comprises processing a neuronal state of the neuron based on the deterministic neural data maintained. Stochastic neural computation comprises generating stochastic neural data relating to the neuron and processing the neuronal state of the neuron based on the stochastic neural data generated.
-
4.发明申请公开(公告)号：US20200074989A1
公开(公告)日：2020-03-05
申请号：US16115258
申请日：2018-08-28
摘要： Low energy deep-learning networks for generating auditory features such as mel frequency cepstral coefficients in audio processing pipelines are provided. In various embodiments, a first neural network is trained to output auditory features such as mel-frequency cepstral coefficients, linear predictive coding coefficients, perceptual linear predictive coefficients, spectral coefficients, filter bank coefficients, and/or spectro-temporal receptive fields based on input audio samples. A second neural network is trained to output a classification based on input auditory features such as mel-frequency cepstral coefficients. An input audio sample is provided to the first neural network. Auditory features such as mel-frequency cepstral coefficients are received from the first neural network. The auditory features such as mel-frequency cepstral coefficients are provided to the second neural network. A classification of the input audio sample is received from the second neural network.
-
5.发明申请公开(公告)号：US20200042856A1
公开(公告)日：2020-02-06
申请号：US16051034
申请日：2018-07-31
发明人： Pallab Datta , Andrew S. Cassidy , Myron D. Flickner , Hartmut Penner , Rathinakumar Appuswamy , Jun Sawada , John V. Arthur , Dharmendra S. Modha , Steven K. Esser , Brian Taba , Jennifer Klamo
摘要： Mapping of neural network layers to physical neural cores is provided. In various embodiments, a neural network description describing a plurality of neural network layers is read. Each of the plurality of neural network layers has an associated weight tensor, input tensor, and output tensor. A plurality of precedence relationships among the plurality of neural network layers is determined. The weight tensor, input tensor, and output tensor of each of the plurality of neural network layers are mapped onto an array of neural cores.
-
公开(公告)号：US20200019836A1
公开(公告)日：2020-01-16
申请号：US16033926
申请日：2018-07-12
发明人： John V. Arthur , Andrew S. Cassidy , Myron D. Flickner , Pallab Datta , Hartmut Penner , Rathinakumar Appuswamy , Jun Sawada , Dharmendra S. Modha , Steven K. Esser , Brian Taba , Jennifer Klamo
摘要： Networks of distributed neural cores are provided with hierarchical parallelism. In various embodiments, a plurality of neural cores is provided. Each of the plurality of neural cores comprises a plurality of vector compute units configured to operate in parallel. Each of the plurality of neural cores is configured to compute in parallel output activations by applying its plurality of vector compute units to input activations. Each of the plurality of neural cores is assigned a subset of output activations of a layer of a neural network for computation. Upon receipt of a subset of input activations of the layer of the neural network, each of the plurality of neural cores computes a partial sum for each of its assigned output activations, and computes its assigned output activations from at least the computed partial sums.
-
公开(公告)号：US20200012929A1
公开(公告)日：2020-01-09
申请号：US16028158
申请日：2018-07-05
发明人： Hartmut Penner , Dharmendra S. Modha , John V. Arthur , Andrew S. Cassidy , Rathinakumar Appuswamy , Pallab Datta , Steven K. Esser , Myron D. Flickner , Jennifer Klamo , Jun Sawada , Brian Taba
摘要： Instruction distribution in an array of neural network cores is provided. In various embodiments, a neural inference chip is initialized with core microcode. The chip comprises a plurality of neural cores. The core microcode is executable by the neural cores to execute a tensor operation of a neural network. The core microcode is distributed to the plurality of neural cores via an on-chip network. The core microcode is executed synchronously by the plurality of neural cores to compute a neural network layer.
-
公开(公告)号：US10282658B2
公开(公告)日：2019-05-07
申请号：US15239642
申请日：2016-08-17
发明人： Rodrigo Alvarez-Icaza Rivera , John V. Arthur , Andrew S. Cassidy , Pallab Datta , Paul A. Merolla , Dharmendra S. Modha
摘要： Embodiments of the invention relate to a neural network system for simulating neurons of a neural model. One embodiment comprises a memory device that maintains neuronal states for multiple neurons, a lookup table that maintains state transition information for multiple neuronal states, and a controller unit that manages the memory device. The controller unit updates a neuronal state for each neuron based on incoming spike events targeting said neuron and state transition information corresponding to said neuronal state.
-
公开(公告)号：US20180103448A1
公开(公告)日：2018-04-12
申请号：US15847530
申请日：2017-12-19
发明人： Rodrigo Alvarez Icaza Rivera , John V. Arthur , Andrew S. Cassidy , Bryan L. Jackson , Paul A. Merolla , Dharmendra S. Modha , Jun Sawada
摘要： Embodiments of the invention provide a system for scaling multi-core neurosynaptic networks. The system comprises multiple network circuits. Each network circuit comprises a plurality of neurosynaptic core circuits. Each core circuit comprises multiple electronic neurons interconnected with multiple electronic axons via a plurality of electronic synapse devices. An interconnect fabric couples the network circuits. Each network circuit has at least one network interface. Each network interface for each network circuit enables data exchange between the network circuit and another network circuit by tagging each data packet from the network circuit with corresponding routing information.
-
10.发明授权公开(公告)号：US09797946B2
公开(公告)日：2017-10-24
申请号：US14946543
申请日：2015-11-19
发明人： Rodrigo Alvarez-Icaza Rivera , John V. Arthur , Andrew S. Cassidy , Bryan L. Jackson , Paul A. Merolla , Dharmendra S. Modha , Jun Sawada
IPC分类号： G01R31/28 , G01R31/317 , G01R31/3177
CPC分类号： G01R31/31703 , G01R31/3172 , G01R31/31725 , G01R31/3177 , G01R31/318516 , G01R31/318519 , G01R31/318558 , G01R31/318561 , G01R31/3187
摘要： Embodiments of the invention provide a scan test system for an integrated circuit comprising multiple processing elements. The system comprises at least one scan input component and at least one scan clock component. Each scan input component is configured to provide a scan input to at least two processing elements. Each scan clock component is configured to provide a scan clock signal to at least two processing elements. The system further comprises at least one scan select component for selectively enabling a scan of at least one processing element. Each processing element is configured to scan in a scan input and scan out a scan output when said the processing element is scan-enabled. The system further comprises an exclusive-OR tree comprising multiple exclusive-OR logic gates. The said exclusive-OR tree generates a parity value representing a parity of all scan outputs scanned out from all scan-enabled processing elements.
-
-
-
-
-
-
-
-
-
搜索结果
117 条记录 (耗时 0.029 秒)