公开(公告)号：US06791931B2

公开(公告)日：2004-09-14

申请号：US09811299

申请日：2001-03-16

申请人： Kenneth J. Eldredge

发明人： Kenneth J. Eldredge

IPC分类号： G01P1518

CPC分类号： B82Y10/00 ,  G11B9/10 ,  G11B9/14 ,  G11B9/1418 ,  G11B33/08 ,  Y10S977/849 ,  Y10S977/861 ,  Y10S977/881

摘要： An accelerometer includes a field emitter to generate an electron beam current and a medium. An effect is generated when the electron beam current bombards the medium. The magnitude of the effect is affected by a physical impact imparting an amount of energy to the accelerometer to cause a relative movement between the field emitter and the medium. The amount of energy imparted to the accelerometer by the physical impact is determined by measuring the magnitude of the effect. The accelerometer can be integrally implemented in a storage device.

摘要翻译： 加速度计包括用于产生电子束电流和介质的场发射器。 当电子束电流轰击介质时产生效果。 效应的大小受到向加速度计赋予能量的物理冲击以引起场发射器和介质之间的相对运动的影响。 通过物理冲击给予加速度计的能量的量通过测量效应的大小来确定。 加速度计可以整体地实现在存储装置中。

公开(公告)号：US06782616B2

公开(公告)日：2004-08-31

申请号：US09759952

申请日：2001-01-12

申请人： Kenneth J. Eldredge

发明人： Kenneth J. Eldredge

IPC分类号： H05K1300

CPC分类号： G06F21/73 ,  G06F21/6245 ,  H05K1/182 ,  Y10T29/4913 ,  Y10T29/49133 ,  Y10T29/49135 ,  Y10T29/49139 ,  Y10T29/49144 ,  Y10T29/49169

摘要： The present disclosure relates to connection arrangements for electrical devices. In the connection arrangements, an electrical device having at least one ledge that includes a plurality of contact terminals provided thereon is electrically connected to an electrical component having a plurality of contacts formed thereon.

摘要翻译： 本公开涉及电气设备的连接装置。 在连接装置中，具有至少一个包括设置在其上的多个接触端子的凸缘的电气装置电连接到其上形成有多个触点的电气部件。

公开(公告)号：US06728799B1

公开(公告)日：2004-04-27

申请号：US09483383

申请日：2000-01-13

申请人： Frederick A. Perner ,  Kenneth J. Eldredge

发明人： Frederick A. Perner ,  Kenneth J. Eldredge

IPC分类号： G06F1314

CPC分类号： G11C7/1006 ,  G11C7/1036 ,  G11C19/00

摘要： Some forms of memory data I/O requires a parallel interface with the memory array and a serial interface with external data ports to the memory. A hybrid decoder/scan register data I/O scheme is described that offers a high speed data access to selected points along a set of scan registers that connect to the columns (bit lines) of a memory array. The interface to the memory array is a long register which comprises a chain of scan register blocks. Data to and from the memory array is transferred in a parallel manner. Data I/O to a specific memory address or memory data block is routed from a serial data I/O line, through a set of switches controlled by a decoder circuit to the input (or output) port of one of the scan register blocks. This hybrid data I/O circuit offers a high speed access to selected points within the column circuits of a memory array while maintaining an efficient and high speed serial output offered by a scan chain data register.

摘要翻译： 存储器数据I / O的一些形式需要与存储器阵列的并行接口以及与存储器的外部数据端口的串行接口。 描述了混合解码器/扫描寄存器数据I / O方案，其提供了沿着连接到存储器阵列的列（位线）的一组扫描寄存器的选定点的高速数据访问。 与存储器阵列的接口是长寄存器，其包括一连串的扫描寄存器块。 往返于存储器阵列的数据以并行方式传送。 特定存储器地址或存储器数据块的数据I / O从串行数据I / O线通过由解码器电路控制的一组开关路由到其中一个扫描寄存器块的输入（或输出）端口。 该混合数据I / O电路提供对存储器阵列的列电路内的选定点的高速访问，同时保持由扫描链数据寄存器提供的有效和高速的串行输出。

公开(公告)号：US06643195B2

公开(公告)日：2003-11-04

申请号：US10044542

申请日：2002-01-11

申请人： Kenneth J. Eldredge ,  Kenneth K. Smith

发明人： Kenneth J. Eldredge ,  Kenneth K. Smith

IPC分类号： G11C700

CPC分类号： G11C11/16 ,  G11C29/76

摘要： An MRAM device includes an array of memory cells. A plurality of traces cross the memory cells. An address decoder coupled to the plurality of traces decodes an address and selects a corresponding subset of the traces. A sparing circuit coupled to the address decoder receives a logical address and outputs a physical address to the address decoder based on memory cell defect information.

公开(公告)号：US06584589B1

公开(公告)日：2003-06-24

申请号：US09498588

申请日：2000-02-04

申请人： Frederick A. Perner ,  Kenneth J. Eldredge ,  Lung Tran

发明人： Frederick A. Perner ,  Kenneth J. Eldredge ,  Lung Tran

IPC分类号： G11C2900

CPC分类号： G11C29/50 ,  G11C27/02 ,  G11C29/02 ,  G11C29/44

摘要： A collection of testing circuits are disclosed which can be used to form a comprehensive built-in test system for MRAM arrays. The combination of testing circuits can detect MRAM array defects including: open rows, shorted memory cells, memory cells which are outside of resistance specifications, and simple read/write pattern errors. The built-in test circuits include a wired-OR circuit connecting all the rows to test for open rows and shorted memory cells. A dynamic sense circuit detects whether the resistance of memory cells is within specified limits. An exclusive-OR gate combined with global write controls is integrated into the sense amplifiers and is used to perform simple read-write pattern tests. Error data from the margin tests and the read-write tests are reported through a second wired-OR circuit. Outputs from the two wired-OR circuits and the associated row addresses are reported to the test processor or recorded into an on-chip error status table.

摘要翻译： 公开了一系列测试电路，可用于形成用于MRAM阵列的综合内置测试系统。 测试电路的组合可以检测MRAM阵列缺陷，包括：开放行，短路存储单元，超出电阻规格的存储单元，以及简单的读/写模式错误。 内置的测试电路包括连接所有行的线OR电路，以测试打开的行和短路存储单元。 动态感测电路检测存储器单元的电阻是否在规定的范围内。 与全局写入控制相结合的异或门被集成到读出放大器中，用于执行简单的读写模式测试。 来自裕度测试和读写测试的错误数据通过第二个有线电路报告。 来自两个有线OR电路和相关行地址的输出被报告给测试处理器或记录在片上错误状态表中。