公开(公告)号：US06918282B2

公开(公告)日：2005-07-19

申请号：US10401207

申请日：2003-03-27

申请人： Seyed R. Zarabadi

发明人： Seyed R. Zarabadi

IPC分类号： G01P15/125 ,  G01P21/00

CPC分类号： G01P15/125 ,  G01P21/00 ,  G01P2015/0814 ,  Y10T29/49

摘要： A test circuit and method provide testing of a capacitive type microsensor. The method includes applying a first signal having a first voltage potential to an input of a microsensor during a non-test operating mode. The method also includes applying a second voltage signal having a second voltage potential different than the first voltage potential during a test mode. The second voltage potential induces a net differential electrostatic force in the microsensor. The method further includes the steps of monitoring an output signal of the microsensor, comparing the output signal to an expected value when the microsensor is in the test mode, and determining if the microsensor is functioning properly as a function of the comparison.

摘要翻译： 测试电路和方法提供电容式微型传感器的测试。 该方法包括在非测试操作模式期间将具有第一电压电位的第一信号应用于微传感器的输入端。 该方法还包括在测试模式期间施加具有与第一电压电位不同的第二电压电位的第二电压信号。 第二电压电位在微传感器中引起净微分静电力。 该方法还包括以下步骤：监测微传感器的输出信号，当微传感器处于测试模式时将输出信号与预期值进行比较，以及根据比较确定微传感器是否正常工作。

公开(公告)号：US5491443A

公开(公告)日：1996-02-13

申请号：US183706

申请日：1994-01-21

申请人： Seyed R. Zarabadi

发明人： Seyed R. Zarabadi

IPC分类号： H03F3/50 ,  H03K17/687

CPC分类号： H03F3/505

摘要： A low-input capacitance self-biased CMOS buffer amplifier (10) which buffers a low-amplitude capacitively coupled output of a sensor to subsequent output circuitry. The buffer amplifier (10) includes a buffer stage (12) which includes an input FET (16) whose gate terminal is connected to the output of the sensor. In order to eliminate the gate-to-source, gate-to-drain and gate-to-substrate capacitances of the input FET (16), various FETs are associated with the buffer stage (12) are interconnected such that the integrity of the input signal is maintained. An output FET (18) has its source terminal connected to the source terminal of the input FET (16). Additionally, a tail cascoded current source (20, 22) is connected to the source terminals of the input and output FETs (16, 18) such that the gate-to-source voltages of these two FETs (16, 18) is the same. The gate terminal and the drain terminal of the output FET (18) are connected such that the input and output FETs (16, 18) act as unit to gain amplifier. The gate terminal of the output FET (18) is connected to two other FETs (24, 26) which transfer the gate-to-drain voltage of the output FET (18) to the drain terminal of the input FET (16). In order to eliminate the gate-to-substrate capacitance, the gate terminal of the input FET (16) is shielded from the substrate by a bottom metal layer (28) of this FET (16). Several self-biasing features are provided to interconnect the FETs in the circuit such that a common current flow is maintained throughout the buffer stage (12).

摘要翻译： 低输入电容自偏置CMOS缓冲放大器（10），其缓冲传感器的低振幅电容耦合输出到后续的输出电路。 缓冲放大器（10）包括缓冲级（12），其包括输入FET（16），其栅极端子连接到传感器的输出端。 为了消除输入FET（16）的栅极到源极，栅极到漏极和栅极到衬底的电容，与缓冲器级（12）相关联的各种FET被互连，使得 输入信号被维持。 输出FET（18）的源极端子连接到输入FET（16）的源极端子。 另外，尾串联电流源（20,22）连接到输入和输出FET（16,18）的源极端子，使得这两个FET（16,18）的栅极 - 源极电压相同 。 输出FET（18）的栅极端子和漏极端子被连接成使得输入和输出FET（16,18）充当增益放大器的单元。 输出FET（18）的栅极端子连接到将输出FET（18）的栅极 - 漏极电压转移到输入FET（16）的漏极端子的另外两个FET（24,26）。 为了消除栅极到衬底的电容，通过FET（16）的底部金属层（28）将输入FET（16）的栅极端子与衬底隔离。 提供了几个自偏置特征以互连电路中的FET，使得在整个缓冲级（12）中保持共同的电流。

公开(公告)号：US5151625A

公开(公告)日：1992-09-29

申请号：US610233

申请日：1990-11-08

申请人： Seyed R. Zarabadi ,  Mohammed I. El-Naggar ,  Nabil I. Khachab

发明人： Seyed R. Zarabadi ,  Mohammed I. El-Naggar ,  Nabil I. Khachab

IPC分类号： H03D7/12 ,  H03D7/14

CPC分类号： H03D7/145 ,  H03D7/1491 ,  H03D2200/0019 ,  H03D2200/0025 ,  H03D2200/0033 ,  H03D2200/0043 ,  H03D7/125

摘要： A voltage to current converter, voltage multiplier and mixer circuit. At least two differential output, common source, pairs of matched field effect transistors have cross connected drains. Those transistors which do not have their drains connected together have their gates connected together to form a first pair of voltage input nodes. The two cross connections form output nodes providing differential output currents. A pair of impedance transformation, low output impedance, buffer amplifiers have bipolar transistor output stages and a high input field effect transistor input stage. The outputs of the output stages are each respectively connected to a different one of the common sources of the differential connected pairs. The input nodes of the input stages form a second pair of voltage input nodes. A low impedance, bipolar transistor, constant dc current, biasing circuit is connected to the common sources for biasing the field effect transistors of the differential pairs in their saturation region and for biasing the bipolar transistors in their active region.

摘要翻译： 电压电流转换器，电压倍增器和混频器电路。 至少两个差分输出，共源，匹配场效应晶体管对具有交叉连接的漏极。 那些没有其漏极连接在一起的晶体管的栅极连接在一起形成第一对电压输入节点。 两个交叉连接形成输出节点，提供差分输出电流。 一对阻抗变换，低输出阻抗，缓冲放大器具有双极晶体管输出级和高输入场效应晶体管输入级。 输出级的输出分别分别连接到差分连接对的公共源中的不同的一个。 输入级的输入节点形成第二对电压输入节点。 低阻抗双极晶体管，恒定直流电流，偏置电路连接到公共源，用于偏置其饱和区域中的差分对的场效应晶体管，以及用于在其有源区中偏置双极晶体管。

公开(公告)号：US4975953A

公开(公告)日：1990-12-04

申请号：US296563

申请日：1989-01-13

申请人： Richard A. Kennedy ,  Gregory J. Manlove ,  Jeffrey J. Marrah ,  Seyed R. Zarabadi

发明人： Richard A. Kennedy ,  Gregory J. Manlove ,  Jeffrey J. Marrah ,  Seyed R. Zarabadi

IPC分类号： H04R3/04 ,  H03G3/34 ,  H04B1/10 ,  H04H20/88 ,  H04S1/00

CPC分类号： H03G3/345

摘要： An FM stereo radio circuit has an ultrasonic noise detector and an amplitude noise detector each for detecting impulse noise by developing an average noise signal and comparing the average noise signal with an attenuated value of the instantaneous noise signal to generate a noise flag. A dual mode circuit normally operates as a low pass filter for a deemphasis function and is switched by the noise flag to operate as a sample and hold circuit which blanks the noise pulse. The dual mode circuit uses a switched capacitance design and is driven by clock signals to serve as a filter. The clock signals are stopped by the noise flag to effect the sample and hold function.

公开(公告)号：US4970472A

公开(公告)日：1990-11-13

申请号：US402042

申请日：1989-09-01

申请人： Richard A. Kennedy ,  Seyed R. Zarabadi

发明人： Richard A. Kennedy ,  Seyed R. Zarabadi

IPC分类号： H03L7/18 ,  H03J5/02 ,  H03L7/089 ,  H03L7/093

CPC分类号： H03L7/0898 ,  H03J5/0281

摘要： A Phase Locked Loop (PLL) circuit includes a compensation circuit which corrects for non-linear sensitivity of a varactor of a voltage controlled oscillator (VCO) which is part of the circuit. The varactor is employed as a capacitance tuning element. The compensation circuit controls the sensitivity of a charging/discharging circuit (a charge pump) of the PLL circuit with a feedback signal which is derived from an input to the VCO. The sensitivity characteristic of the charge pump is made the complement of the non-linear portion of the VCO sensitivity characteristic.