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    Apparatus and method to reduce signal cross-talk
    31.
    发明授权
    Apparatus and method to reduce signal cross-talk 失效
    降低信号串扰的装置和方法

    公开(公告)号：US07038319B2

    公开(公告)日：2006-05-02

    申请号：US10644372

    申请日：2003-08-20

    申请人： Patrick H. Buffet ,  Charles S. Chiu ,  Jon D. Garlett ,  Louis L. Hsu ,  Brian J. Schuh

    发明人： Patrick H. Buffet ,  Charles S. Chiu ,  Jon D. Garlett ,  Louis L. Hsu ,  Brian J. Schuh

    IPC分类号： H01L23/48

    CPC分类号： H01L23/642 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/3025 ,  H01L2224/05599

    摘要： A semiconductor chip package with reduced cross-talk between adjacent signals in a layer of a carrier is disclosed. A first pair of conductors for carrying a first signal is provided in a layer of the carrier. A second pair of conductors for carrying a second signal is provided adjacent to the first pair of conductors in the layer, where the first and second pairs of conductors are configured such that cross-talk between the first and second pairs of conductors is substantially minimized, without increasing the size of the package. The height of the first pair of conductors is shorter than the second pair of conductors. Alternatively, the first and second pairs of conductors are configured so that they evenly affect each other. The chip package thus reduces the cross-talk without compromising the density of the interconnections in the package or resulting in an increase in the size of the package.

    摘要翻译： 公开了一种在载体层中的相邻信号之间的串扰减小的半导体芯片封装。 用于承载第一信号的第一对导体提供在载体的层中。 用于承载第二信号的第二对导体被提供为邻近层中的第一对导体，其中第一和第二对导体被配置为使得第一和第二对导体之间的串扰基本上最小化， 而不会增加包装的尺寸。 第一对导体的高度比第二对导体短。 或者，第一和第二对导体被配置成使得它们彼此均匀地影响。 芯片封装因此减少串扰，而不会影响封装中互连的密度，或导致封装尺寸的增加。

    Integrated circuit I/O interface that uses excess data I/O pin bandwidth to input control signals or output status information
    37.
    发明授权
    Integrated circuit I/O interface that uses excess data I/O pin bandwidth to input control signals or output status information 失效
    集成电路I / O接口，使用多余的数据I / O引脚带宽来输入控制信号或输出状态信息

    公开(公告)号：US6031767A

    公开(公告)日：2000-02-29

    申请号：US718108

    申请日：1996-09-18

    申请人： Brian J. Schuh ,  Christopher Philip Parker ,  Vinay V. Shah

    发明人： Brian J. Schuh ,  Christopher Philip Parker ,  Vinay V. Shah

    IPC分类号： G06F13/12 ,  G11C19/00 ,  G06F13/00

    CPC分类号： G06F13/126

    摘要： An I/O interface for an integrated circuit (IC) is described that has a reduced number of I/O pins dedicated to providing control signals to or status information from the IC. In one embodiment, the IC comprises a plurality of input pins connected to logic for receiving and processing input data. The input pins have an input bandwidth greater than the logic's processing rate. If data and control signals are multiplexed onto the same input pin, the excess input pin bandwidth may used to transfer control signals into a plurality of latches within the IC. The I/O interface outputs a select signal that designates when an external device should drive the input pins with either data or control signals. In a specific embodiment, the logic comprises a parallel to serial converter and the control signal select conversion speed or encoding options. In another embodiment, the IC comprises a plurality of output pins connected to the output of a selector. Status latches and logic for outputting processed data drive the selector's inputs. The IC outputs a select signal that allows an external device to determine when the output pins are carrying processed data versus status information and thus demultiplex the signals. In a specific embodiment, the logic is a serial to parallel converter. Finally, both the input and output pin embodiments may used together in a single IC.

    摘要翻译： 描述了用于集成电路（IC）的I / O接口，其具有减少数量的专用于向IC提供控制信号或从IC提供状态信息的I / O引脚。 在一个实施例中，IC包括连接到用于接收和处理输入数据的逻辑的多个输入引脚。 输入引脚的输入带宽大于逻辑处理速率。 如果数据和控制信号被复用到相同的输入引脚上，则可以使用多余的输入引脚带宽将控制信号传送到IC内的多个锁存器。 I / O接口输出选择信号，指定外部设备何时用数据或控制信号驱动输入引脚。 在具体实施例中，逻辑包括并行到串行转换器和控制信号选择转换速度或编码选项。 在另一个实施例中，IC包括连接到选择器的输出的多个输出引脚。 用于输出处理后数据的状态锁存器和逻辑驱动选择器的输入。 IC输出选择信号，允许外部设备确定输出引脚何时承载处理的数据与状态信息，从而解复用信号。 在具体实施例中，逻辑是串并转换器。 最后，输入和输出引脚实施例都可以在单个IC中一起使用。