公开(公告)号：US20240312889A1

公开(公告)日：2024-09-19

申请号：US18345426

申请日：2023-06-30

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Fang-Lin TSAI ,  Wei-Son TSAI ,  Kun-Yuan LUO ,  Pei-Geng WENG ,  Ching-Hung TSENG

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/49838 ,  H01L23/3107 ,  H01L23/49822 ,  H01L24/16 ,  H01L2224/16157 ,  H01L2224/16168 ,  H01L2924/15174 ,  H01L2924/3511

Abstract: An electronic package and a circuit structure thereof are provided, in which a circuit layer and an electrical function part are formed on a dielectric layer of the circuit structure, and the dielectric layer has at least one corner at a right angle, where a shape of the electrical function part at the corner and corresponding to the right angle is of a non-right angle shape and/or a routing path of the circuit layer at the corner and corresponding to the right angle is of a non-right angle shape, so that stress concentration can be reduced, thereby preventing the electronic package from warping.

公开(公告)号：US12068324B2

公开(公告)日：2024-08-20

申请号：US17358790

申请日：2021-06-25

Applicant: Apple Inc.

Inventor： Jared L. Zerbe ,  Emerson S. Fang ,  Jun Zhai ,  Shawn Searles

IPC: H01L27/10 ,  H01G4/228 ,  H01L23/00 ,  H01L23/13 ,  H01L23/48 ,  H01L23/498 ,  H01L23/64 ,  H01L25/065 ,  H01L25/16 ,  H01L25/18 ,  H01L49/02 ,  H01L23/50 ,  H01L25/10

CPC classification number: H01L27/101 ,  H01G4/228 ,  H01L23/13 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/642 ,  H01L24/14 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/18 ,  H01L28/40 ,  H01L23/49827 ,  H01L23/50 ,  H01L24/16 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/13025 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16265 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/1033 ,  H01L2924/12042 ,  H01L2924/1205 ,  H01L2924/1427 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/15153 ,  H01L2924/15159 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/157 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19103 ,  H01L2924/19104 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2924/15311 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00 ,  H01L2924/12042 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2924/00014 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device package is described that includes a power consuming device (such as an SOC device). The power consuming device may include one or more current consuming elements. A passive device may be coupled to the power consuming device. The passive device may include a plurality of passive elements formed on a semiconductor substrate. The passive elements may be arranged in an array of structures on the semiconductor substrate. The power consuming device and the passive device may be coupled using one or more terminals. The passive device and power consuming device coupling may be configured in such a way that the power consuming device determines functionally the way the passive device elements will be used.

公开(公告)号：US20240170385A1

公开(公告)日：2024-05-23

申请号：US18145198

申请日：2022-12-22

Applicant: InnoLux Corporation

Inventor： Te-Hsun LIN ,  Wen-Hsiang LIAO ,  Mei-Yen CHEN ,  Ming-Hsien SHIH ,  Yung-Feng CHEN ,  Cheng-Chi WANG

IPC: H01L23/498 ,  H01L23/31

CPC classification number: H01L23/49838 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L2924/15174

Abstract: A semiconductor package device is provided. The semiconductor package device includes a chip and a redistribution layer disposed on the chip and electrically connected to the chip. The redistribution layer includes a plurality of first metal lines and a plurality of second metal lines, wherein at least one of the second metal lines is disposed between two adjacent first metal lines. The included angle between the at least one of the second metal lines and the two adjacent first metal lines is greater than or equal to 0 degrees and less than or equal to 10 degrees. The first width of one of the two adjacent first metal lines is greater than the second width of the at least one of the second metal lines.

公开(公告)号：US20240162132A1

公开(公告)日：2024-05-16

申请号：US18384152

申请日：2023-10-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kwangsoo KIM

IPC: H01L23/498 ,  H01L23/00 ,  H01L25/10

CPC classification number: H01L23/49822 ,  H01L23/49838 ,  H01L24/16 ,  H01L25/105 ,  H01L24/48 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/48229 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15174 ,  H01L2924/182

Abstract: Provided is a semiconductor package including a semiconductor chip, a connection structure below the semiconductor chip and electrically connected to the semiconductor chip, and an external connection terminal below the connection structure, wherein the connection structure includes a first via array including a plurality of first vias in a first direction, a second via array above the first via array and including a plurality of second vias in the first direction, and a first pad between the first via array and the second via array and on upper surfaces of the plurality of the first vias, wherein the second via array is offset from the first via array in the first direction and does not overlap the first via array in a vertical direction.

公开(公告)号：US20240153856A1

公开(公告)日：2024-05-09

申请号：US18386003

申请日：2023-11-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joonghyun BAEK ,  Hyunsoo CHUNG ,  Dongok KWAK ,  Eunjeong IM

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L25/10 ,  H10B80/00

CPC classification number: H01L23/49822 ,  H01L23/3107 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/73 ,  H01L25/105 ,  H10B80/00 ,  H01L24/32 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/1441 ,  H01L2924/15174 ,  H01L2924/15184 ,  H01L2924/15311

Abstract: A semiconductor package having a lower redistribution structure includes a redistribution insulation layer, a plurality of ball pads in the redistribution insulation layer apart from one another, a double via which includes a first active via and a dummy via located on at least one of the plurality of ball pads and apart from each other in the redistribution insulation layer, and a first active redistribution layer electrically connected to the first active via in the redistribution insulation layer, solder balls electrically connected to the plurality of ball pads under the lower redistribution structure, a first semiconductor chip on the lower redistribution structure and electrically connected to the first active via and the first active redistribution layer of the lower redistribution structure, and a molding layer molding the first semiconductor chip on the lower redistribution structure.

公开(公告)号：US20240120266A1

公开(公告)日：2024-04-11

申请号：US18369258

申请日：2023-09-18

Applicant: SAMSUNG-RO, YEONGTONG-GU

Inventor： Sujung HYUNG ,  Myoungchul EUM ,  Chiwoo LEE

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/29 ,  H01L23/31 ,  H01L25/10

CPC classification number: H01L23/49838 ,  H01L23/295 ,  H01L23/3107 ,  H01L23/49822 ,  H01L23/49866 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15174 ,  H01L2924/35121

Abstract: Provided is a semiconductor package including a first distribution structure, which includes a plurality of first distribution patterns disposed between a plurality of first lower surface connection pads and a plurality of first upper surface connection pads, and a first base insulating layer surrounding the plurality of first distribution patterns. The semiconductor package further includes a second distribution structure including a plurality of second distribution patterns disposed between a plurality of second lower surface connection pads and a plurality of second upper surface connection pads, and a second base insulating layer surrounding the plurality of second distribution patterns. The semiconductor package further includes a plurality of connection structures configured to penetrate the encapsulant and disposed adjacent to the semiconductor chip, wherein the connection structure includes a conductive antioxidant layer covering side surfaces of the conductive post.

公开(公告)号：US20240112974A1

公开(公告)日：2024-04-04

申请号：US18320513

申请日：2023-05-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Min Sek Jang

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/498 ,  H01L25/10

CPC classification number: H01L23/3135 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/08 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/08235 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15174

Abstract: A semiconductor package includes a first redistribution structure including a first redistribution layer, a first semiconductor chip on the first redistribution structure, an insulating layer adjacent a sidewall of the first semiconductor chip on the first redistribution structure and spaced apart from the first semiconductor chip in a horizontal direction, a connection structure extending through the insulating layer in a vertical direction and electrically connected to the first redistribution layer, a first molding layer on a sidewall and a top surface of the first semiconductor chip, and a second molding layer directly on each of a top surface of the insulating layer and a top surface of the first molding layer. The second molding layer includes a material different from a material of the first molding layer, and the top surface of the first semiconductor chip is lower than the top surface of the insulating layer.

公开(公告)号：US20240079393A1

公开(公告)日：2024-03-07

申请号：US18218673

申请日：2023-07-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngdeuk KIM ,  Heejung HWANG

IPC: H01L25/10 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L23/498 ,  H01L23/538 ,  H10B80/00

CPC classification number: H01L25/105 ,  H01L23/3135 ,  H01L23/3675 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5386 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H10B80/00 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/15153 ,  H01L2924/15174

Abstract: A semiconductor package includes a package substrate including a substrate cavity, the substrate cavity extending from an upper surface of the package substrate toward a lower surface of the package substrate, a wiring interposer attached to the package substrate, a memory semiconductor structure attached to a lower surface of the wiring interposer, at least a portion of the memory semiconductor structure art being accommodated in the substrate cavity, a logic semiconductor chip attached to an upper surface of the wiring interposer, a conductive spacer spaced apart from the logic semiconductor chip in a horizontal direction, the conductive spacer being attached to the upper surface of the wiring interposer and overlapping the memory semiconductor structure in a vertical direction, and a heat dissipation member over the logic semiconductor chip and the conductive spacer.

公开(公告)号：US20240055338A1

公开(公告)日：2024-02-15

申请号：US18218885

申请日：2023-07-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byungho KIM ,  Youngchan KO ,  Gyeongho KIM ,  Yongkoon LEE ,  Myungdo CHO ,  Sangseok HONG

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/49822 ,  H01L23/3128 ,  H01L23/49827 ,  H01L24/16 ,  H01L24/48 ,  H01L24/32 ,  H01L24/08 ,  H01L2924/15174 ,  H01L2924/13091 ,  H01L2924/01029 ,  H01L2924/01022 ,  H01L2224/16165 ,  H01L2224/16055 ,  H01L2224/48108 ,  H01L2224/48145 ,  H01L2224/32054 ,  H01L2224/32146 ,  H01L2224/32235 ,  H01L2224/08135

Abstract: A fan-out semiconductor package includes a wiring substrate including a first fan-in region, a fan-out region surrounding the first fan-in region, and a second fan-in region, a first fan-in chip structure, a second fan-in chip structure, a first redistribution structure including first redistribution elements disposed on a bottom surface of the wiring substrate, and a second redistribution structure disposed on a top surface of the wiring substrate, and a chip wiring structure formed on a top surface of the second chip, and the second redistribution structure includes a second redistribution layer extending to the first fan-in region and the fan-out region, a plurality of second redistribution vias integrally formed with the second redistribution layer and extending downward, and a seed layer surrounding the second redistribution layer and bottom surfaces of the plurality of second redistribution vias.

公开(公告)号：US11848294B2

公开(公告)日：2023-12-19

申请号：US17552550

申请日：2021-12-16

Applicant: Intel Corporation

Inventor： Christoph Kutter ,  Ewald Soutschek ,  Georg Meyer-Berg

IPC: H01L23/00 ,  H01L23/538 ,  H01L21/683 ,  H01L23/48 ,  H01L23/12 ,  H01L23/50 ,  H01L21/56

CPC classification number: H01L24/14 ,  H01L21/6835 ,  H01L23/12 ,  H01L23/48 ,  H01L23/50 ,  H01L23/5381 ,  H01L23/5389 ,  H01L24/06 ,  H01L24/19 ,  H01L24/96 ,  H01L21/568 ,  H01L2224/02 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/92 ,  H01L2924/014 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01068 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/15313 ,  H01L2924/181 ,  H01L2924/19015 ,  H01L2924/19042 ,  H01L2924/19104 ,  H01L2224/92 ,  H01L2224/96 ,  H01L2224/82 ,  H01L2924/181 ,  H01L2924/00

Abstract: A semiconductor device including a semiconductor chip having a first conduction element; a substrate having second and third conduction elements; and external connection elements configured to form an electrical path between the second and third conduction elements via the first conduction element.