SCHEDULING THREADS IN MULTIPROCESSOR COMPUTER
    31.
    发明申请
    SCHEDULING THREADS IN MULTIPROCESSOR COMPUTER 失效
    在多处理器计算机中安排螺纹

    公开(公告)号:US20120260257A1

    公开(公告)日:2012-10-11

    申请号:US13528645

    申请日:2012-06-20

    IPC分类号: G06F9/46 G06F13/24

    CPC分类号: G06F9/5027 G06F9/4812

    摘要: A computer program product for scheduling threads in a multiprocessor computer comprises computer program instructions configured to select a thread in a ready queue to be dispatched to a processor and determine whether an interrupt mask flag is set in a thread control block associated with the thread. If the interrupt mask flag is set in the thread control block associated with the thread, the computer program instructions are configured to select a processor, set a current processor priority register of the selected processor to least favored, and dispatch the thread from the ready queue to the selected processor.

    摘要翻译: 一种用于在多处理器计算机中调度线程的计算机程序产品包括计算机程序指令,其被配置为选择准备队列中的线程以分派到处理器,并且确定是否在与线程相关联的线程控制块中设置了中断屏蔽标志。 如果在与线程相关联的线程控制块中设置了中断屏蔽标志,则将计算机程序指令配置为选择处理器,将所选处理器的当前处理器优先级寄存器设置为最不利,并将线程从就绪队列 到所选择的处理器。

    Optimized preemption and reservation of software locks for woken threads
    32.
    发明授权
    Optimized preemption and reservation of software locks for woken threads 失效
    优化抢占线程的软件锁的抢占和预留

    公开(公告)号:US08261279B2

    公开(公告)日:2012-09-04

    申请号:US12049304

    申请日:2008-03-15

    IPC分类号: G06F9/46

    CPC分类号: G06F9/526 G06F2209/522

    摘要: An approach is provided that reserves a software lock for a waiting thread is presented. When a software lock is released by a first thread, a second thread that is waiting for the same resource controlled by the software lock is woken up. In addition, a reservation to the software lock is established for the second thread. After the reservation is established, if the lock is available and requested by a thread other than the second thread, the requesting thread is denied, added to the wait queue, and put to sleep. In addition, the reservation is cleared. After the reservation has been cleared, the lock will be granted to the next thread to request the lock.

    摘要翻译: 提供了一种保留用于等待线程的软件锁的方法。 当软件锁由第一个线程释放时,等待软件锁定的相同资源的第二个线程被唤醒。 另外,针对第二线程建立对软件锁定的预约。 在建立预留之后,如果第二线程之外的线程可用并请求该锁,则请求线程被拒绝,被添加到等待队列中并进入休眠状态。 此外,预订已被清除。 预订清除后,锁将被授予下一个线程以请求锁定。

    FILE IDENTIFICATION AND RETRIEVAL IN DIRECTORIES FOR CATEGORIZED FILES
    33.
    发明申请
    FILE IDENTIFICATION AND RETRIEVAL IN DIRECTORIES FOR CATEGORIZED FILES 失效
    分类文件目录中的文件识别和检索

    公开(公告)号:US20120191751A1

    公开(公告)日:2012-07-26

    申请号:US13430288

    申请日:2012-03-26

    IPC分类号: G06F17/30

    摘要: A system and computer program product are provided for marking a file. Responsive to a file being received, the file is stored in a directory in a file system. An indicia is associated with the file and the directory. The file is displayed using the indicia as a marked file and the directory is displayed using the indicia as a marked directory.

    摘要翻译: 提供了用于标记文件的系统和计算机程序产品。 响应于正在接收的文件,该文件存储在文件系统中的目录中。 标记与文件和目录相关联。 使用标记将文件显示为标记文件,并使用标记将目录显示为标记目录。

    Method and apparatus for instruction trace registers
    34.
    发明授权
    Method and apparatus for instruction trace registers 有权
    指令跟踪寄存器的方法和装置

    公开(公告)号:US07844859B2

    公开(公告)日:2010-11-30

    申请号:US11924192

    申请日:2007-10-25

    IPC分类号: G06F11/00

    CPC分类号: G06F9/30101

    摘要: A computer implemented method, apparatus, and computer usable program product for utilizing instruction trace registers. In one embodiment, a value in a target processor register in a plurality of processor registers is updated in response to executing an instruction associated with program code. In response to updating the value in the target processor register, an address for the instruction is copied from an instruction address register into an instruction trace register associated with the target processor register. The instruction trace register holds the address of the instruction that updated the value stored in the target processor register.

    摘要翻译: 一种用于使用指令跟踪寄存器的计算机实现的方法,装置和计算机可用程序产品。 在一个实施例中,响应于执行与程序代码相关联的指令,更新多个处理器寄存器中的目标处理器寄存器中的值。 响应更新目标处理器寄存器中的值,将指令的地址从指令地址寄存器复制到与目标处理器寄存器相关联的指令跟踪寄存器中。 指令跟踪寄存器保存更新存储在目标处理器寄存器中的值的指令的地址。

    Memory pacing
    35.
    发明授权
    Memory pacing 失效
    记忆起搏

    公开(公告)号:US07788455B2

    公开(公告)日:2010-08-31

    申请号:US12478830

    申请日:2009-06-05

    IPC分类号: G06F12/00

    摘要: A method, system, and program for managing memory page requests in a multi-processor data processing system determines a threshold value of available memory, and dynamically adjusts an allocation time to fulfill a page request if the available memory is below a threshold value. The allocation time to fulfill the page request is based upon a percentage of available memory pages once a page stealer commences a scan for pages. An allocation wait time is inversely proportionally adjusted depending upon the percentage of available memory. The allocation wait time has a duration that increases in time as the percentage of available memory decreases and decreases in time as the percentage of available memory increases. More specifically, an average time per page to allocate a page including a scan time for the scan in computing the average time is determined. Then a tunable value is applied to the average time to determine a wait time. In a preferred embodiment, user defined values are received that would control the allocation wait time before fulfilling a page request.

    摘要翻译: 用于管理多处理器数据处理系统中的存储器页面请求的方法,系统和程序确定可用存储器的阈值,并且如果可用存储器低于阈值,则动态地调整分配时间以满足页面请求。 一旦页面窃取器开始扫描页面,则完成页面请求的分配时间基于可用内存页面的百分比。 分配等待时间根据可用内存的百分比进行反比例调整。 分配等待时间具有随时间增加的持续时间,随着可用内存的百分比的增加,可用内存的百分比随时间而减少。 更具体地,确定在计算平均时间时分配包括用于扫描的扫描时间的页面的每页的平均时间。 然后将可调值应用于平均时间以确定等待时间。 在优选实施例中,接收用户定义的值,其将在满足页面请求之前控制分配等待时间。

    E-Mail Response Time Estimation on Compose or Send
    36.
    发明申请
    E-Mail Response Time Estimation on Compose or Send 失效
    撰写或发送的电子邮件响应时间估计

    公开(公告)号:US20100017484A1

    公开(公告)日:2010-01-21

    申请号:US12176665

    申请日:2008-07-21

    IPC分类号: G06F15/16

    CPC分类号: G06Q10/107

    摘要: An e-mail application calculates a dynamic estimate of an e-mail response time. A recipient address module, a status module, a processing module, and a presentation module interact to generate a first and a second estimated response time. The first estimated response time is determined from sender side data. The second estimated response time is generated using recipient mailbox status data after the e-mail is received by the recipient. The second estimated response time is used to dynamically update the estimated response time displayed to the sender.

    摘要翻译: 电子邮件应用程序计算电子邮件响应时间的动态估计。 接收者地址模块,状态模块,处理模块和呈现模块交互以产生第一和第二估计响应时间。 第一个估计的响应时间由发送方数据确定。 在收件人收到电子邮件之后,使用收件人邮箱状态数据生成第二个估计的响应时间。 第二估计响应时间用于动态地更新显示给发送者的估计响应时间。

    On-type biometrics fingerprint soft keyboard
    37.
    发明授权
    On-type biometrics fingerprint soft keyboard 失效
    On-type生物识别指纹软键盘

    公开(公告)号:US07486810B1

    公开(公告)日:2009-02-03

    申请号:US12108510

    申请日:2008-04-24

    IPC分类号: G06K9/00

    CPC分类号: G06F21/32

    摘要: One embodiment of this invention addresses the use of biometrics for accessing a touch screen keyboard on a tablet personal computer (PC), and ensuring security if the PC is left unattended. The core idea is to assign biometrics to soft keyboards without the use of a physical keyboard. In this example, every key on the keyboard will be assigned a biometric fingerprint associated with the corresponding finger that would type it. When a user types, a portion of its fingerprint touches the keys. By storing the portions and assigning the portions to the soft keyboard, it is ensured that every key typed is associated with the corresponding key fingerprint portion, thus ensuring maximum biometric security. In addition, the keystroke delays and word delays can be recorded and compared with previous data for added security.

    摘要翻译: 本发明的一个实施例解决了使用生物识别技术来访问平板电脑个人计算机(PC)上的触摸屏键盘,以及如果PC无人值守,则确保安全性。 核心思想是将生物识别分配给软键盘,而无需使用物理键盘。 在该示例中,键盘上的每个键将被分配与将键入它的相应手指相关联的生物测定指纹。 当用户键入时,其指纹的一部分触摸键。 通过存储部分并将部分分配给软键盘,确保每个键入的键都与相应的键指纹部分相关联,从而确保最大的生物特征安全性。 此外,可以记录击键延迟和字延迟,并与先前的数据进行比较以增加安全性。

    Scheduling Threads In Multiprocessor Computer
    38.
    发明申请
    Scheduling Threads In Multiprocessor Computer 失效
    在多处理器计算机中调度线程

    公开(公告)号:US20080184246A1

    公开(公告)日:2008-07-31

    申请号:US12059461

    申请日:2008-03-31

    IPC分类号: G06F9/46

    CPC分类号: G06F9/5027 G06F9/4812

    摘要: Methods, systems, and computer program products are provided for scheduling threads in a multiprocessor computer. Embodiments include selecting a thread in a ready queue to be dispatched to a processor and determining whether an interrupt mask flag is set in a thread control block associated with the thread. If the interrupt mask flag is set in the thread control block associated with the thread, embodiments typically include selecting a processor, setting a current processor priority register of the selected processor to least favored, and dispatching the thread from the ready queue to the selected processor. In some embodiments, setting the current processor priority register of the selected processor to least favored is carried out by storing a value associated with the highest interrupt priority in the current processor priority register.

    摘要翻译: 提供方法,系统和计算机程序产品用于在多处理器计算机中调度线程。 实施例包括选择要发送到处理器的准备队列中的线程,并且确定是否在与线程相关联的线程控制块中设置了中断屏蔽标志。 如果在与线程相关联的线程控制块中设置中断屏蔽标志,则实施例通常包括选择处理器,将所选择的处理器的当前处理器优先级寄存器设置为最不利,并将线程从就绪队列调度到所选择的处理器 。 在一些实施例中,将所选择的处理器的当前处理器优先级寄存器设置为最不利的是通过在当前处理器优先级寄存器中存储与最高中断优先级相关联的值来执行。

    Scheduling Threads In A Multi-Processor Computer
    39.
    发明申请
    Scheduling Threads In A Multi-Processor Computer 有权
    在多处理器计算机中调度线程

    公开(公告)号:US20080178183A1

    公开(公告)日:2008-07-24

    申请号:US12055179

    申请日:2008-03-25

    IPC分类号: G06F9/46

    CPC分类号: G06F9/4812

    摘要: Scheduling threads in a multi-processor computer system including establishing an interrupt threshold for a thread, where the interrupt threshold represents a maximum permissible number of interrupts during thread execution on a processor; executing the thread on a current processor, where the thread has thread affinity for one or more processors including the current processor; counting a number of interrupts during execution of the thread on the current processor; and removing thread affinity for the current processor in dependence upon the counted number of interrupts and the interrupt threshold.

    摘要翻译: 在多处理器计算机系统中调度线程,包括建立线程的中断阈值,其中中断阈值表示在处理器上的线程执行期间的最大允许中断次数; 在当前处理器上执行线程,其中线程对于包括当前处理器的一个或多个处理器具有线程亲和性; 在当前处理器上的线程执行期间对多个中断进行计数; 并根据计数的中断次数和中断阈值去除当前处理器的线程亲和度。

    System and method for scheduling compatible threads in a simultaneous multi-threading processor using cycle per instruction value occurred during identified time interval
    40.
    发明授权
    System and method for scheduling compatible threads in a simultaneous multi-threading processor using cycle per instruction value occurred during identified time interval 有权
    用于在同步多线程处理器中调度兼容线程的系统和方法,使用在指定时间间隔期间的每个指令值周期

    公开(公告)号:US07360218B2

    公开(公告)日:2008-04-15

    申请号:US10671132

    申请日:2003-09-25

    CPC分类号: G06F9/4881 G06F2209/483

    摘要: A system and method for identifying compatible threads in a Simultaneous Multithreading (SMT) processor environment is provided by calculating a performance metric, such as cycles per instruction (CPI), that occurs when two threads are running on the SMT processor. The CPI that is achieved when both threads were executing on the SMT processor is determined. If the CPI that was achieved is better than the compatibility threshold, then information indicating the compatibility is recorded. When a thread is about to complete, the scheduler looks at the run queue from which the completing thread belongs to dispatch another thread. The scheduler identifies a thread that is (1) compatible with the thread that is still running on the SMT processor (i.e., the thread that is not about to complete), and (2) ready to execute. The CPI data is continually updated so that threads that are compatible with one another are continually identified.

    摘要翻译: 通过计算在SMT处理器上运行两个线程时发生的性能指标(例如每个指令周期(CPI)),可以提供用于在同时多线程(SMT)处理器环境中识别兼容线程的系统和方法。 确定在两个线程在SMT处理器上执行时实现的CPI。 如果实现的CPI优于兼容性阈值,则记录指示兼容性的信息。 当线程即将完成时,调度程序将查看完成线程所属的运行队列,以调度另一个线程。 调度程序标识(1)与SMT处理器上仍然运行的线程(即,即将完成的线程)兼容的线程,以及(2)准备执行。 持续更新CPI数据,以便不断地识别彼此兼容的线程。