公开(公告)号：US20090141533A1

公开(公告)日：2009-06-04

申请号：US11946938

申请日：2007-11-29

申请人： Deok-kee Kim ,  Chandrasekharan Kothandaraman ,  Dan Moy ,  Norman W. Robson ,  John M. Safran ,  Kenneth J. Stein

发明人： Deok-kee Kim ,  Chandrasekharan Kothandaraman ,  Dan Moy ,  Norman W. Robson ,  John M. Safran ,  Kenneth J. Stein

IPC分类号： G11C17/08 ,  H01L27/20 ,  H01L21/768

CPC分类号： H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

摘要： A metal layer and a semiconductor layer are sequentially deposited on a substrate. The semiconductor layer and the metal layer are lithographically patterned to form a stack of a semiconductor portion and a metal gate portion, which is preferably performed concurrently with formation of at least one metal gate stack. In one embodiment, the size of the semiconductor portion is reduced and a metal semiconductor alloy portion is formed on the semiconductor portion by metallization. In a first electrical antifuse formed thereby, the metal semiconductor alloy portion may be electromigrated to form a short between the metal semiconductor alloy portion and the metal gate portion. In another embodiment, two disjoined metal semiconductor alloy portions are formed on the semiconductor portion. In a second electrical antifuse formed thereby, the metal semiconductor alloy portion may be electromigrated to form a short between the two previously disjoined metal semiconductor alloy portions.

摘要翻译： 金属层和半导体层顺序地沉积在基板上。 半导体层和金属层被光刻图案化以形成半导体部分和金属栅极部分的堆叠，其优选地与至少一个金属栅极叠层的形成同时进行。 在一个实施例中，半导体部分的尺寸减小，并且金属半导体合金部分通过金属化形成在半导体部分上。 在由此形成的第一电反熔丝中，金属半导体合金部分可以电铸以在金属半导体合金部分和金属栅极部分之间形成短路。 在另一个实施例中，在半导体部分上形成两个非接合的金属半导体合金部分。 在由此形成的第二电反熔丝中，金属半导体合金部分可以被电铸以在两个先前接合的金属半导体合金部分之间形成短路。

公开(公告)号：US07492008B2

公开(公告)日：2009-02-17

申请号：US10896812

申请日：2004-07-22

申请人： Stephen Richard Fox ,  Neena Garg ,  Kenneth John Giewont ,  Junedong Lee ,  Siegfried Lutz Maurer ,  Dan Moy ,  Maurice Heathcote Norcott ,  Devendra Kumar Sadana

发明人： Stephen Richard Fox ,  Neena Garg ,  Kenneth John Giewont ,  Junedong Lee ,  Siegfried Lutz Maurer ,  Dan Moy ,  Maurice Heathcote Norcott ,  Devendra Kumar Sadana

IPC分类号： H01L21/336

CPC分类号： H01L21/76243

摘要： A method for forming a semiconductor-on-insulator (SOI) substrate is described incorporating the steps of heating a substrate, implanting oxygen into a heated substrate, cooling the substrate, implanting into a cooled substrate and annealing. The steps of implanting may be at several energies to provide a plurality of depths and corresponding buried damaged regions. Prior to implanting, the step of cleaning the substrate surface and/or forming a patterned mask thereon may be performed. The invention overcomes the problem of raising the quality of buried oxide and its properties such as surface roughness, uniform thickness and breakdown voltage Vbd.

摘要翻译： 描述了一种用于形成绝缘体上半导体（SOI）衬底的方法，其包括加热衬底，将氧注入加热衬底，冷却衬底，注入冷却衬底和退火的步骤。 植入的步骤可以是几种能量以提供多个深度和相应的埋入损伤区域。 在植入之前，可以执行清洁衬底表面和/或在其上形成图案化掩模的步骤。 本发明克服了提高掩埋氧化物质量及其性能如表面粗糙度，均匀厚度和击穿电压Vbd的问题。

公开(公告)号：US06538299B1

公开(公告)日：2003-03-25

申请号：US09678315

申请日：2000-10-03

申请人： Young H. Kwark ,  Dan Moy ,  Mark B. Ritter ,  Dennis L. Rogers ,  Jeffrey J. Welser

发明人： Young H. Kwark ,  Dan Moy ,  Mark B. Ritter ,  Dennis L. Rogers ,  Jeffrey J. Welser

IPC分类号： H01L31075

CPC分类号： H01L31/1804 ,  H01L31/02327 ,  H01L31/02363 ,  H01L31/03529 ,  H01L31/101 ,  Y02E10/547 ,  Y02P70/521

摘要： A semiconductor device (and method for forming the device) includes a silicon-on-insulator (SOI) wafer formed on a substrate surface. An isolation trench in the wafer surface surrounds alternating p-type trenches and n-type trenches and electrically isolates the device from the substrate, thereby allowing the device to be effectively utilized as a differential detector in an optoelectronic circuit.

摘要翻译： 半导体器件（以及用于形成器件的方法）包括在衬底表面上形成的绝缘体上硅（SOI）晶片。 晶片表面中的隔离沟槽围绕交替的p型沟槽和n型沟槽，并将器件与衬底电隔离，从而允许器件有效地用作光电子电路中的差分检测器。

公开(公告)号：US5418188A

公开(公告)日：1995-05-23

申请号：US755471

申请日：1991-09-05

申请人： James M. E. Harper ,  Dan Moy ,  Shahrnaz Motakef

发明人： James M. E. Harper ,  Dan Moy ,  Shahrnaz Motakef

IPC分类号： H01L21/285 ,  H01L21/441 ,  H01L21/302

CPC分类号： H01L21/28518 ,  Y10S438/913

摘要： A method for controlled positioning of a compound layer such as TiSi.sub.2 or CoSi.sub.2 in a multilayer device such as a semiconductor is disclosed. The compound surface layer is situated adjacent to an intermediate layer comprised of one of the two types of atoms present in the molecules of the adjacent compound surface layer. The intermediate layer is also situated adjacent to a base layer, such as a semiconductor substrate. An epitaxial silicon layer is the suggested intermediate layer where the surface layer is comprised of TiSi.sub.2 or CoSi.sub.2. By simultaneously heating the multilayer device and using an appropriate etching process for selectively removing the atoms from the surface of the compound surface layer which are common in both the compound and intermediate layer (i.e., silicon) the intermediate layer can be reduced in thickness and/or fully consumed while the structural integrity of the compound surface layer remains essentially unchanged. This results in positioning the surface layer directly adjacent to the base layer, thus allowing for the controlled placement of the compound layer in the multilayer device.

摘要翻译： 公开了一种在诸如半导体的多层器件中控制定位诸如TiSi 2或CoSi 2的化合物层的方法。 复合表面层位于由相邻化合物表面层的分子中存在的两种原子中的一种构成的中间层附近。 中间层也位于与基底层相邻的位置，例如半导体衬底。 外延硅层是建议的中间层，其中表面层由TiSi 2或CoSi 2组成。 通过同时加热多层器件并使用适当的蚀刻工艺来选择性地从化合物和中间层（即硅）中的化合物表面层的表面除去原子，中间层的厚度和/ 或完全消耗，同时复合表面层的结构完整性保持基本不变。 这导致将表面层直接邻近基底层定位，从而允许化合物层在多层器件中的受控放置。