公开(公告)号：US08159272B2

公开(公告)日：2012-04-17

申请号：US12498164

申请日：2009-07-06

Applicant: Kallol Chatterjee ,  Anurag Tiwari

Inventor： Kallol Chatterjee ,  Anurag Tiwari

IPC: H03K9/08

CPC classification number: G01R31/31709

Abstract: An apparatus for measuring time interval between two selected edges of a clock signal. includes an edge generator, a first multi-tap delay module, a second multi-tap delay module, and a multi-element phase detector. The edge generator produces a first edge at a first output node and a second selected edge at a second output node. First multi-tap delay module provides a first constant incremental delay at each tap to the first edge. Second multi-tap delay module provides a second constant incremental delay at each tap to the second selected edge. Each element of the multi-element phase detector has a first input terminal and a second input terminal. The first input terminal is coupled to a selected tap of the first multi-tap delay module and the second input terminal is coupled to a corresponding tap of the second multi-tap delay module. The output terminals of the multi-element phase detector provide the value of the time interval.

Abstract translation: 用于测量时钟信号的两个选择的边缘之间的时间间隔的装置包括边缘发生器，第一多抽头延迟模块，第二多抽头延迟模块和多元件相位检测器。 边缘发生器在第一输出节点处产生第一边缘，并在第二输出节点处产生第二选择边缘。 第一多抽头延迟模块在每个抽头处向第一边沿提供第一恒定的增量延迟。 第二多抽头延迟模块在每个抽头对第二选定边缘提供第二恒定增量延迟。 多元件相位检测器的每个元件具有第一输入端和第二输入端。 第一输入端耦合到第一多抽头延迟模块的选定抽头，第二输入端耦合到第二多抽头延迟模块的对应抽头。 多元件相位检测器的输出端提供时间间隔的值。

公开(公告)号：US07304513B2

公开(公告)日：2007-12-04

申请号：US11213436

申请日：2005-08-26

Applicant: Kallol Chatterjee ,  Deependra Jain

Inventor： Kallol Chatterjee ,  Deependra Jain

IPC: H03K21/00 ,  H03K23/00 ,  H03K25/00

CPC classification number: H03K23/665 ,  H03K21/40 ,  H03K23/667

Abstract: A programmable high-speed frequency divider is provided in which a stage for forming a frequency divider, which is capable of being programmed with a programmable dividing ratio, is simplified in order to reduce the area and circuit complexity. The programmable frequency divider includes a first synchronizing element coupled to an output of a logic detection circuit for generating a synchronized divider output, an additional synchronizing element coupled to the output of the logic detection circuit for receiving its clock from the output of a divide-by-two circuit and generating a special synchronized load output, and combinational logic blocks that receive the load output and generate load signals for bit-cells for detecting the state of all stages. Preferably, start-up circuitry is included within the frequency divider to ensure that the frequency-divider never goes into a false state.

Abstract translation: 提供了一种可编程高速分频器，其中用于形成能够以可编程分频比编程的分频器的级被简化以便减小面积和电路复杂度。 可编程分频器包括耦合到逻辑检测电路的输出的第一同步元件，用于产生同步的分频器输出;耦合到逻辑检测电路的输出的附加同步元件，用于从分频输出接收其时钟 两个电路并产生一个特殊的同步负载输出，以及接收负载输出的组合逻辑块，并产生位单元的负载信号，以检测所有级的状态。 优选地，启动电路包括在分频器内，以确保分频器不会进入假状态。

公开(公告)号：US20070229175A1

公开(公告)日：2007-10-04

申请号：US11638306

申请日：2006-12-12

Applicant: Nitin Agarwal ,  Kallol Chatterjee

Inventor： Nitin Agarwal ,  Kallol Chatterjee

IPC: H03L7/00

CPC classification number: H03L7/0891 ,  H03L7/093

Abstract: The invention relates to an improved phase locked loop (PLL) circuit for preventing erroneous condition in the charge pump operation. The invention includes modification in the PLL circuitry by adding delay elements for connection between the phase frequency detector and the charge pump and a digital logic circuit for obtaining the clock signals for the loop filter.

Abstract translation: 本发明涉及一种用于防止电荷泵操作中的错误状态的改进的锁相环（PLL）电路。 本发明包括通过添加用于相位频率检测器和电荷泵之间的连接的延迟元件和用于获得环路滤波器的时钟信号的数字逻辑电路来修改PLL电路。

公开(公告)号：US07259605B2

公开(公告)日：2007-08-21

申请号：US10969783

申请日：2004-10-20

Applicant: Kallol Chatterjee ,  Jeet Narayan Tiwari

Inventor： Kallol Chatterjee ,  Jeet Narayan Tiwari

IPC: H03K3/356

CPC classification number: H03K3/356121

Abstract: A pseudo true single phase clock latch (pseudo “TSPC” latch) includes additional circuitry coupled to three previously floating nodes that can lose data depending upon the amount of leakage current associated with these nodes. The additional circuitry, including a positive feedback circuit, improves the performance of a true single phase clock latch circuit at lower frequencies without significant degradation in high frequency operation of the latch.

Abstract translation: 伪真实单相时钟锁存器（伪“TSPC”锁存器）包括耦合到三个先前浮动节点的附加电路，其可以根据与这些节点相关联的泄漏电流的数量而丢失数据。 包括正反馈电路的附加电路在较低频率下改善了真正的单相时钟锁存电路的性能，而不会在锁存器的高频操作中显着降级。

公开(公告)号：US20060164151A1

公开(公告)日：2006-07-27

申请号：US11286276

申请日：2005-11-22

Applicant: Kallol Chatterjee ,  Samala Sreekiran

Inventor： Kallol Chatterjee ,  Samala Sreekiran

IPC: H01L35/00

CPC classification number: G05F3/242

Abstract: A first order temperature compensated reference current generator includes a current device providing a controlled current, a startup circuit connected to the current device for initiating operation of the current device, and a current definition mechanism driven by the current device for supplying a current which is independent of temperature, process and individual temperature coefficients circuit elements used. The current definition mechanism incorporates voltage controlled resistors driven by a predetermined voltage and having a predetermined temperature coefficient.

Abstract translation: 第一阶温度补偿参考电流发生器包括提供受控电流的电流装置，连接到当前装置的启动电路，用于启动当前装置的操作，以及由当前装置驱动的用于提供独立电流的电流的电流定义机构 的温度，工艺和各个温度系数电路元件。 目前的定义机构包含由预定电压驱动并具有预定温度系数的压控电阻。

公开(公告)号：US20060082405A1

公开(公告)日：2006-04-20

申请号：US10969783

申请日：2004-10-20

Applicant: Kallol Chatterjee ,  Jeet Tiwari

Inventor： Kallol Chatterjee ,  Jeet Tiwari

IPC: H03K3/037

CPC classification number: H03K3/356121

Abstract: A pseudo true single phase clock latch (pseudo “TSPC” latch) includes additional circuitry coupled to three previously floating nodes that can lose data depending upon the amount of leakage current associated with these nodes. The additional circuitry, including a positive feedback circuit, improves the performance of a true single phase clock latch circuit at lower frequencies without significant degradation in high frequency operation of the latch.

Abstract translation: 伪真实单相时钟锁存器（伪“TSPC”锁存器）包括耦合到三个先前浮动节点的附加电路，其可以根据与这些节点相关联的泄漏电流的数量而丢失数据。 包括正反馈电路的附加电路在较低频率下改善了真正的单相时钟锁存电路的性能，而不会在锁存器的高频操作中显着降级。

公开(公告)号：US20050270110A1

公开(公告)日：2005-12-08

申请号：US11146930

申请日：2005-06-06

Applicant: Kallol Chatterjee ,  Samala Sreekiran

Inventor： Kallol Chatterjee ,  Samala Sreekiran

IPC: H03L7/00 ,  H03L7/099 ,  H03L7/18

CPC classification number: H03L7/0995 ,  H03L7/18

Abstract: A VCO buffer circuit comprising a first loading means receiving a first signal for loading the VCO at a first input node; a second loading means receiving a second signal for loading the VCO at a second input node; a third loading means coupled to said first loading means for loading the VCO at third input node to thereby balance a load distribution on three nodes of VCO. At least three current controlling means are coupled to each other to form a symmetrical configuration and receive input signals from said first and second loading means for minimizing variations in the oscillation frequency of the VCO. A buffering means is connected to the output of the controlling means for buffering the output of the current controlling means.

Abstract translation: 一种VCO缓冲电路，包括第一加载装置，其接收用于在第一输入节点加载VCO的第一信号; 第二加载装置，在第二输入节点处接收用于加载所述VCO的第二信号; 耦合到所述第一加载装置的第三加载装置，用于在第三输入节点处加载VCO，从而平衡VCO的三个节点上的负载分布。 至少三个电流控制装置彼此耦合以形成对称配置，并且从所述第一和第二负载装置接收输入信号，以最小化VCO振荡频率的变化。 缓冲装置连接到控制装置的输出端，用于缓冲电流控制装置的输出。