公开(公告)号：US5706474A

公开(公告)日：1998-01-06

申请号：US455155

申请日：1995-05-31

Applicant: Kan Takeuchi ,  Masashi Horiguchi ,  Masakazu Aoki ,  Takeshi Sakata ,  Hitoshi Tanaka ,  Katsumi Matsuno

Inventor： Kan Takeuchi ,  Masashi Horiguchi ,  Masakazu Aoki ,  Takeshi Sakata ,  Hitoshi Tanaka ,  Katsumi Matsuno

IPC: G11C11/407 ,  G06F12/00 ,  G06F13/16 ,  G11C7/10 ,  G11C11/401 ,  G11C11/409

CPC classification number: G11C7/1072 ,  G06F13/1689 ,  Y02B60/1228

Abstract: A memory system is provided which is capable of eliminating deterioration in a processing rate due to possible signal delays between an input/output circuit and memory blocks. Complication of design is also reduced, especially when the scale and chip area of the memory system increase. A memory chip includes a plurality of memory array blocks each including an address buffer and an address counter, and operates on the basis of a local clock cycle. A control circuit is synchronous with a clock of an external device, and synchronous data-transfer circuitry includes a buffer which modulates the transfer rate of serial data which arrives from a memory array block at a local clock cycle so as to be synchronous with the clock of the control circuit. External clock signal lines are not distributed to the memory array blocks.

Abstract translation: 提供了一种能够消除由于输入/输出电路和存储块之间的信号延迟引起的处理速率恶化的存储器系统。 设计的复杂性也降低了，特别是当存储器系统的规模和芯片面积增加时。 存储器芯片包括多个存储器阵列块，每个存储器阵列块包括地址缓冲器和地址计数器，并且基于本地时钟周期进行操作。 控制电路与外部设备的时钟同步，同步数据传输电路包括一个缓冲器，该缓冲器调制在本地时钟周期从存储器阵列块到达的串行数据的传输速率，以便与时钟同步 的控制电路。 外部时钟信号线不分配给存储器阵列块。

公开(公告)号：US5539279A

公开(公告)日：1996-07-23

申请号：US362239

申请日：1994-12-22

Applicant: Kan Takeuchi ,  Masashi Horiguchi ,  Masakazu Aoki ,  Katsumi Matsuno ,  Takeshi Sakata ,  Jun Etoh ,  Yoshinobu Nakagome

Inventor： Kan Takeuchi ,  Masashi Horiguchi ,  Masakazu Aoki ,  Katsumi Matsuno ,  Takeshi Sakata ,  Jun Etoh ,  Yoshinobu Nakagome

IPC: G11C11/22

CPC classification number: G11C11/22

Abstract: A highly reliable and high speed ferroelectric memory having a high degree of integration. In a ferroelectric memory having a multiple of memory cells M1, each constituted by one transistor and one ferroelectric capacitor, in the normal operation, the ferroelectric memory is used as a volatile memory in which a voltage on a storage node ST1 stores information in a DRAM mode. Both the electric potential at the plate PL1 of the ferroelectric capacitor and a precharge electric potential on a data line DL1(j) are Vcc/2. When the a power supply voltage is turned on, a polarization state is detected as a ferroelectric memory of a plate electric potential of Vcc/2 and a precharge electric potential of Vss (or Vcc) and the read operation is performed a FERAM mode. The switching between the DRAM mode and the FERAM mode is executed by generating a signal to designate the FERAM mode in the memory along with the turn-on of the power supply and by generating a signal to designate the DRAM mode after completion of the conversion operation from nonvolatile information to volatile information.

Abstract translation: 具有高度集成度的高可靠性和高速铁电存储器。 在具有由一个晶体管和一个铁电电容器构成的多个存储单元M1的铁电存储器中，在正常操作中，铁电存储器用作其中存储节点ST1上的电压将信息存储在DRAM中的易失性存储器 模式。 强电介质电容器的板PL1的电位和数据线DL1（j）的预充电电位都为Vcc / 2。 当电源电压接通时，偏振状态被检测为Vcc / 2的电位电压和Vss（或Vcc）的预充电电位的铁电存储器，并且读取操作被执行FERAM模式。 DRAM模式和FERAM模式之间的切换通过产生一个信号来指示存储器中的FERAM模式以及电源的导通，并且在完成转换操作之后产生指定DRAM模式的信号 从非易失性信息到易失性信息。