公开(公告)号：US5539279A

公开(公告)日：1996-07-23

申请号：US362239

申请日：1994-12-22

申请人： Kan Takeuchi ,  Masashi Horiguchi ,  Masakazu Aoki ,  Katsumi Matsuno ,  Takeshi Sakata ,  Jun Etoh ,  Yoshinobu Nakagome

发明人： Kan Takeuchi ,  Masashi Horiguchi ,  Masakazu Aoki ,  Katsumi Matsuno ,  Takeshi Sakata ,  Jun Etoh ,  Yoshinobu Nakagome

IPC分类号： G11C11/22

CPC分类号： G11C11/22

摘要： A highly reliable and high speed ferroelectric memory having a high degree of integration. In a ferroelectric memory having a multiple of memory cells M1, each constituted by one transistor and one ferroelectric capacitor, in the normal operation, the ferroelectric memory is used as a volatile memory in which a voltage on a storage node ST1 stores information in a DRAM mode. Both the electric potential at the plate PL1 of the ferroelectric capacitor and a precharge electric potential on a data line DL1(j) are Vcc/2. When the a power supply voltage is turned on, a polarization state is detected as a ferroelectric memory of a plate electric potential of Vcc/2 and a precharge electric potential of Vss (or Vcc) and the read operation is performed a FERAM mode. The switching between the DRAM mode and the FERAM mode is executed by generating a signal to designate the FERAM mode in the memory along with the turn-on of the power supply and by generating a signal to designate the DRAM mode after completion of the conversion operation from nonvolatile information to volatile information.

摘要翻译： 具有高度集成度的高可靠性和高速铁电存储器。 在具有由一个晶体管和一个铁电电容器构成的多个存储单元M1的铁电存储器中，在正常操作中，铁电存储器用作其中存储节点ST1上的电压将信息存储在DRAM中的易失性存储器 模式。 强电介质电容器的板PL1的电位和数据线DL1（j）的预充电电位都为Vcc / 2。 当电源电压接通时，偏振状态被检测为Vcc / 2的电位电压和Vss（或Vcc）的预充电电位的铁电存储器，并且读取操作被执行FERAM模式。 DRAM模式和FERAM模式之间的切换通过产生一个信号来指示存储器中的FERAM模式以及电源的导通，并且在完成转换操作之后产生指定DRAM模式的信号 从非易失性信息到易失性信息。

公开(公告)号：US5955896A

公开(公告)日：1999-09-21

申请号：US606852

申请日：1996-02-26

申请人： Masashi Horiguchi ,  Jun Etoh ,  Takeshi Sakata ,  Kan Takeuchi ,  Katsumi Matsuno ,  Masakazu Aoki

发明人： Masashi Horiguchi ,  Jun Etoh ,  Takeshi Sakata ,  Kan Takeuchi ,  Katsumi Matsuno ,  Masakazu Aoki

IPC分类号： H03K19/0175 ,  G11C11/407 ,  G11C11/408 ,  H03K5/24 ,  H03K5/20

CPC分类号： H03K5/2481

摘要： In an input circuit for semiconductor devices, such as an address buffer, an arrangement is provided which obviates the timing margin from capture of an input signal to its latching and outputting, thereby increasing the operation speed of the input circuit. The address buffer includes a differential amplifier Ai which receives an input signal Ai and outputs a pair of differential signals A-come-first-served latch circuit detects, latches and outputs one of the paired differential signals that has changed first. Activation/inactivation of the differential amplifier is done by turning on and off an N-channel MOS transistor through a Set signal. When activated, the differential amplifier generates a potential difference between the paired differential signals and, when inactivated, has its paired differential signals go low.

摘要翻译： 在诸如地址缓冲器的半导体器件的输入电路中，提供了一种排除了将时序余量从捕获输入信号到其锁存和输出的布置，从而增加了输入电路的操作速度。 地址缓冲器包括差分放大器Ai，其接收输入信号Ai并输出一对差分信号A先来先生的锁存电路检测，锁存和输出首先改变的成对差分信号之一。 差分放大器的激活/失活是通过设置信号来打开和关闭N沟道MOS晶体管来实现的。 当被激活时，差分放大器产生成对的差分信号之间的电位差，当失活时，它的成对差分信号变低。

公开(公告)号：US5706474A

公开(公告)日：1998-01-06

申请号：US455155

申请日：1995-05-31

申请人： Kan Takeuchi ,  Masashi Horiguchi ,  Masakazu Aoki ,  Takeshi Sakata ,  Hitoshi Tanaka ,  Katsumi Matsuno

发明人： Kan Takeuchi ,  Masashi Horiguchi ,  Masakazu Aoki ,  Takeshi Sakata ,  Hitoshi Tanaka ,  Katsumi Matsuno

IPC分类号： G11C11/407 ,  G06F12/00 ,  G06F13/16 ,  G11C7/10 ,  G11C11/401 ,  G11C11/409

CPC分类号： G11C7/1072 ,  G06F13/1689 ,  Y02B60/1228

摘要： A memory system is provided which is capable of eliminating deterioration in a processing rate due to possible signal delays between an input/output circuit and memory blocks. Complication of design is also reduced, especially when the scale and chip area of the memory system increase. A memory chip includes a plurality of memory array blocks each including an address buffer and an address counter, and operates on the basis of a local clock cycle. A control circuit is synchronous with a clock of an external device, and synchronous data-transfer circuitry includes a buffer which modulates the transfer rate of serial data which arrives from a memory array block at a local clock cycle so as to be synchronous with the clock of the control circuit. External clock signal lines are not distributed to the memory array blocks.

摘要翻译： 提供了一种能够消除由于输入/输出电路和存储块之间的信号延迟引起的处理速率恶化的存储器系统。 设计的复杂性也降低了，特别是当存储器系统的规模和芯片面积增加时。 存储器芯片包括多个存储器阵列块，每个存储器阵列块包括地址缓冲器和地址计数器，并且基于本地时钟周期进行操作。 控制电路与外部设备的时钟同步，同步数据传输电路包括一个缓冲器，该缓冲器调制在本地时钟周期从存储器阵列块到达的串行数据的传输速率，以便与时钟同步 的控制电路。 外部时钟信号线不分配给存储器阵列块。

公开(公告)号：US5455786A

公开(公告)日：1995-10-03

申请号：US257542

申请日：1994-06-09

申请人： Kan Takeuchi ,  Katsumi Matsuno ,  Yoshinobu Nakagome ,  Masakazu Aoki

发明人： Kan Takeuchi ,  Katsumi Matsuno ,  Yoshinobu Nakagome ,  Masakazu Aoki

IPC分类号： H01L27/10 ,  G11C11/22 ,  G11C14/00 ,  H01L21/8246 ,  H01L27/105

CPC分类号： G11C11/22

摘要： A highly reliable and high speed ferroelectric memory having high degree of integration is provided. In a ferroelectric memory having a plurality of memory cells M1 each constituted by one transistor and one ferroelectric capacitor. In the normal operation, the ferroelectric memory is used as a volatile memory in which a voltage of a storage node ST1 is utilized as the stored information. Both an electric potential at a plate PL1 of the ferroelectric capacitor and a precharge electric potential on a data line DL1(j) are made Vcc/2.

摘要翻译： 提供了具有高集成度的高可靠性和高速铁电存储器。 在具有由一个晶体管和一个铁电电容器构成的多个存储单元M1的铁电存储器中。 在正常操作中，铁电存储器用作其中使用存储节点ST1的电压作为存储信息的易失性存储器。 铁电电容器的板PL1上的电位和数据线DL1（j）上的预充电电位都为Vcc / 2。

公开(公告)号：US5726930A

公开(公告)日：1998-03-10

申请号：US653236

申请日：1996-05-24

申请人： Masatoshi Hasegawa ,  Kazuhiko Kajigaya ,  Kan Takeuchi ,  Katsumi Matsuno ,  Osamu Nagashima

发明人： Masatoshi Hasegawa ,  Kazuhiko Kajigaya ,  Kan Takeuchi ,  Katsumi Matsuno ,  Osamu Nagashima

IPC分类号： G11C14/00 ,  G11C11/22 ,  G11C11/401 ,  G11C11/404 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

CPC分类号： G11C11/22 ,  G11C11/404

摘要： A semiconductor memory device capable of simultaneously providing volatile and non-volatile portions is disclosed having a plurality of memory mats, and a plurality of plate electrodes and a plurality of memory mats each provided in one-to-one correspondence with the memory maps. The memory mats each include a plurality of word lines, a plurality of bit lines and a plurality of memory cells provided at the intersections of the word lines and the bit lines. The memory cells each include an information storage capacitor having a ferroelectric film, and an address selection MOSFET. The information storage capacitor has a pair of electrodes, one of which is connected to the plate electrode that corresponds to the memory mat in which the information storage capacitor is included. A first voltage or a second voltage is selectively applied to each of the plate electrodes according to data held in the memory circuit corresponding to the plate electrode. When the first voltage is applied to the plate electrode, the information storage capacitors connected to the plate electrode are made incapable of polarization reversal irrespective of a binary write signal given to the bit lines. When the second voltage is applied to the plate electrode, the information storage capacitors connected to the plate electrode are made capable of polarization inversion in response to a binary write signal given to the bit lines.

摘要翻译： 公开了能够同时提供易失性和非易失性部分的半导体存储器件，其具有多个存储器垫，以及多个板电极和多个存储器垫，每个存储垫与存储器映射图一一对应地提供。 存储器垫每个都包括多个字线，多个位线和设置在字线和位线的交点处的多个存储单元。 存储单元各自包括具有铁电膜的信息存储电容器和地址选择MOSFET。 信息存储电容器具有一对电极，其中一个电极连接到对应于包括信息存储电容器的存储器垫的平板电极。 根据与平板电极相对应的存储电路中保存的数据，选择性地向每个平板电极施加第一电压或第二电压。 当第一电压施加到平板电极时，连接到平板电极的信息存储电容器不会产生极化反转，而与给定位线的二进制写入信号无关。 当第二电压施加到平板电极时，连接到平板电极的信息存储电容器响应于给定位线的二进制写入信号而能够进行极化反转。

公开(公告)号：US5615145A

公开(公告)日：1997-03-25

申请号：US580090

申请日：1995-12-20

申请人： Kan Takeuchi ,  Katsumi Matsuno ,  Kazuhiko Kajiyama ,  Osamu Nagashima ,  Masatoshi Hasegawa

发明人： Kan Takeuchi ,  Katsumi Matsuno ,  Kazuhiko Kajiyama ,  Osamu Nagashima ,  Masatoshi Hasegawa

IPC分类号： G11C11/22 ,  G11C14/00 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108

CPC分类号： G11C11/22

摘要： A semiconductor memory which includes a plurality of memory cells each having first and second capacitors connected in series and a field-effect transistor whose source or drain is connected to a node between the first and second capacitors. The memory cells are arranged at intersections of bit lines and word lines thereby forming a matrix. The first capacitor of each memory cell is a ferroelectric capacitor using a ferroelectric material as an insulating film. A plate electrode of the first capacitor of each memory cell is held at a first potential when the memory is operated in a first mode and the plate electrode of the first capacitor is held at a second potential when the memory is operated in a second mode. The first potential is different from the second potential.

摘要翻译： 一种半导体存储器，包括多个存储单元，每个存储单元均具有串联连接的第一和第二电容器，以及源极或漏极连接到第一和第二电容器之间的节点的场效应晶体管。 存储单元布置在位线和字线的交点处，从而形成矩阵。 每个存储单元的第一电容器是使用铁电材料作为绝缘膜的铁电电容器。 当存储器以第一模式操作时，每个存储单元的第一电容器的平板电极被保持在第一电位，并且当存储器在第二模式下操作时，第一电容器的平板电极被保持在第二电位。 第一个潜力与第二个潜力不同。

公开(公告)号：US08165454B2

公开(公告)日：2012-04-24

申请号：US11480043

申请日：2006-06-30

申请人： Shunji Okada ,  Katsumi Matsuno

发明人： Shunji Okada ,  Katsumi Matsuno

IPC分类号： G11B27/00 ,  H04N5/93

CPC分类号： G11B20/10527 ,  G06F12/0246 ,  G06F2212/7203 ,  G11B27/102 ,  G11B27/3027 ,  G11B2020/10675 ,  G11B2220/17 ,  G11B2220/2562 ,  H04N1/2166 ,  H04N5/765 ,  H04N5/772 ,  H04N5/85 ,  H04N5/907 ,  H04N9/7921 ,  H04N9/8042 ,  H04N9/8063 ,  H04N9/8205 ,  H04N2101/00 ,  H04N2201/216

摘要： The present invention efficiently executes a transfer process from a flash memory to an optical disc. A recording control apparatus includes a UDF file system section that configures a UDF file system on the flash file system of a flash memory and an application format section that converts video and audio data into a file group conforming to the DVD application format and manages it on the UDF file system. When copying the data recorded in the flash memory to a DVD, a management information switching section of the apparatus converts the logical addresses of the flash memory into the logical addresses of the DVD. A DVD buffer control section converts the data recorded in an array of 64 Kbytes that is the recording unit of the flash memory into an array of 32 Kbytes that is the recording unit of the DVD and transfers them to the DVD drive.

摘要翻译： 本发明有效地执行从闪存到光盘的传送处理。 记录控制装置包括：UDF文件系统部分，其在闪存的闪存文件系统上配置UDF文件系统;以及应用格式部分，其将视频和音频数据转换为符合DVD应用格式的文件组，并将其管理 UDF文件系统。 当将记录在闪存中的数据复制到DVD时，该装置的管理信息切换部将闪存的逻辑地址转换为DVD的逻辑地址。 DVD缓冲器控制部分将作为闪存的记录单元的64K字节阵列中记录的数据转换为作为DVD的记录单元的32K字节的数组，并将它们传送到DVD驱动器。

公开(公告)号：US07738765B2

公开(公告)日：2010-06-15

申请号：US10737984

申请日：2003-12-17

申请人： Katsumi Matsuno ,  Kenichiro Aridome ,  Osamu Date

发明人： Katsumi Matsuno ,  Kenichiro Aridome ,  Osamu Date

IPC分类号： H04N5/91

CPC分类号： G11B27/034 ,  G11B27/11 ,  G11B27/3027 ,  G11B27/329 ,  G11B27/34 ,  G11B2220/218 ,  G11B2220/2562 ,  H04N5/765 ,  H04N5/772 ,  H04N5/85 ,  H04N5/9201 ,  H04N5/9205

摘要： An information recording apparatus is disclosed which comprises: a first recording element for recording input picture information in units of recording into a first area of a recording medium; a representative data generating element for generating representative data representing the picture information recorded in the units of recording; a first memory for recording a plurality of symbolic pictures; a second memory for recording a program for generating link information linking the plurality of symbolic pictures recorded in the first memory with the representative data; a link information generating element for generating the link information using program; a picture generating element which, based on the link information, generates picture information including at least the symbolic pictures and the representative data being linked with one another; and a second recording element for recording the picture information generated by the picture generating element to a second area of the recording medium.

摘要翻译： 公开了一种信息记录装置，包括：第一记录元件，用于以记录单位将输入图像信息记录到记录介质的第一区域中; 用于产生表示以记录为单位记录的图像信息的代表数据的代表性数据产生元件; 用于记录多个符号图像的第一存储器; 第二存储器，用于记录用于生成将记录在第一存储器中的多个符号图像链接到代表数据的链接信息的程序; 用于使用程序生成链接信息的链接信息生成元件; 图像生成元件，其基于所述链接信息生成至少包括所述符号图像和所述代表性数据彼此链接的图像信息; 以及第二记录元件，用于将由图像生成元件生成的图像信息记录到记录介质的第二区域。

公开(公告)号：US07188244B2

公开(公告)日：2007-03-06

申请号：US10174094

申请日：2002-06-17

申请人： Katsumi Matsuno

发明人： Katsumi Matsuno

IPC分类号： H04L9/12

CPC分类号： H04L63/0869 ,  H04L2463/121 ,  H04W12/06 ,  H04W28/18 ,  H04W52/0254 ,  H04W84/18 ,  Y02D70/144

摘要： In order to drive a PC and a cam-coder communicating with each other by adopting a Bluetooth technique to carry out mutual authentication processing, the user presses an authentication button of the PC and an authentication button of the cam-coder simultaneously. An authentication program of the PC detects an on time to turn on the authentication button of the PC and an off time to turn off the button. Likewise, an authentication program of the cam-coder detects an on time to turn on the authentication button of the cam-coder and an off time to turn off the button. The detected on and off times are exchanged between the PC and the cam-coder. If a difference between the on times and a difference between the off times are each found to be within a predetermined range, a result of the mutual authentication processing is considered to be positive. In this way, the mutual authentication processing can be carried out with ease.

摘要翻译： 为了驱动通过采用蓝牙技术进行相互认证处理的彼此通信的PC和摄像机，用户同时按下PC的认证按钮和摄像机的认证按钮。 PC的认证程序检测到打开PC的认证按钮的打开时间，并关闭时间以关闭按钮。 同样，凸轮编码器的认证程序检测接通时间以打开摄像机的认证按钮，并关闭时间以关闭按钮。 在PC和摄像机之间交换检测到的开关时间。 如果每次发现接通时间和关闭时间之间的差别在预定范围内，则认为相互认证处理的结果为肯定。 以这种方式，可以容易地执行相互认证处理。

公开(公告)号：US20050078945A1

公开(公告)日：2005-04-14

申请号：US10485424

申请日：2003-05-23

申请人： Kenichiro Aridome ,  Shingo Yoshioka ,  Katsumi Matsuno ,  Akinobu Sugino

发明人： Kenichiro Aridome ,  Shingo Yoshioka ,  Katsumi Matsuno ,  Akinobu Sugino

IPC分类号： G11B20/10 ,  G11B7/0045 ,  G11B7/007 ,  G11B20/12 ,  G11B27/00 ,  G11B27/034 ,  G11B27/32 ,  H04N5/781

CPC分类号： G11B27/329 ,  G11B27/034 ,  G11B2020/1873 ,  G11B2220/216 ,  G11B2220/218 ,  G11B2220/2562

摘要： This invention is a recording medium recording method for an optical disc or the like. Every time one VTS is prepared, padding processing is executed to secure a recording area for new TMP_VMGI following that VTS and for VTSI and VTSM VOBS of the subsequent title. As, every time one VTS is prepared, new TMP_VMGI following that VTS is recorded, TMP_VMGI is recorded at the position that is added to the number of VTSs. Therefore, even when the management information becomes unreadable because of update exceeding the rewriting durability of the medium with respect to the recording area of TMP_VMGI on the innermost side, the management information can be read from TMP_VMGI recorded in the other recording areas and the finalizing processing can be executed.

摘要翻译： 本发明是用于光盘等的记录介质记录方法。 每次准备一个VTS时，执行填充处理以保护跟随该VTS的新的TMP_VMGI的记录区域以及后续标题的VTSI和VTSM VOBS。 因为，每当一个VTS准备好时，记录VTS之后的新的TMP_VMGI，则在添加到VTS的数量的位置记录TMP_VMGI。 因此，即使管理信息由于相对于最内侧的TMP_VMGI的记录区域的更新超过介质的重写耐久性而变得不可读，也可以从记录在其他记录区域的TMP_VMGI中读取管理信息，并且完成处理 可以执行。