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44 条记录 (耗时 0.037 秒)

    Plural Differential Pair Employing FinFET Structure
    31.
    发明申请
    Plural Differential Pair Employing FinFET Structure 有权
    采用FinFET结构的多个差分对

    公开(公告)号：US20130341733A1

    公开(公告)日：2013-12-26

    申请号：US13532422

    申请日：2012-06-25

    申请人： Karl R. Erickson ,  Phil C. Paone ,  David P. Paulsen ,  John E. Sheets ,  Gregory J. Uhlmann ,  Kelly L. Williams

    发明人： Karl R. Erickson ,  Phil C. Paone ,  David P. Paulsen ,  John E. Sheets ,  Gregory J. Uhlmann ,  Kelly L. Williams

    IPC分类号： H01L27/088 ,  H01L21/20

    CPC分类号： H01L21/823431 ,  H01L21/823475 ,  H01L27/0886 ,  H01L27/1211

    摘要： A plural differential pair may include a first semiconductor fin having first and second drain areas. First and second body areas may be disposed on the fin between the first and second drain areas. A source area may be disposed on the fin between the first and second body areas. The plural differential pair may include a first pair of fin field effect (FinFET) transistors and a second pair of FinFET transistors. The plural differential pair may include first and second top fin areas projecting from respective portions of a top side of the first and second body areas of the fin. The first and second top fin areas may each have a width that is wider than the first and second body areas of the fin.

    摘要翻译： 多个差分对可以包括具有第一和第二漏极区域的第一半导体鳍片。 第一和第二主体区域可以设置在第一和第二排水区域之间的翅片上。 源区域可以设置在第一和第二身体区域之间的翅片上。 多个差分对可以包括第一对鳍场效应（FinFET）晶体管和第二对FinFET晶体管。 多个差分对可以包括从翅片的第一和第二主体区域的顶侧的相应部分突出的第一和第二顶部翅片区域。 第一和第二顶鳍区域可以各自具有比翅片的第一和第二身体区域宽的宽度。

    Plural differential pair employing FinFET structure
    32.
    发明授权
    Plural differential pair employing FinFET structure 有权
    采用FinFET结构的多个差分对

    公开(公告)号：US09018713B2

    公开(公告)日：2015-04-28

    申请号：US13532422

    申请日：2012-06-25

    申请人： Karl R. Erickson ,  Phil C. Paone ,  David P. Paulsen ,  John E. Sheets ,  Gregory J. Uhlmann ,  Kelly L. Williams

    发明人： Karl R. Erickson ,  Phil C. Paone ,  David P. Paulsen ,  John E. Sheets ,  Gregory J. Uhlmann ,  Kelly L. Williams

    IPC分类号： H01L27/088 ,  H01L21/8234 ,  H01L27/12

    CPC分类号： H01L21/823431 ,  H01L21/823475 ,  H01L27/0886 ,  H01L27/1211

    摘要： A plural differential pair may include a first semiconductor fin having first and second drain areas. First and second body areas may be disposed on the fin between the first and second drain areas. A source area may be disposed on the fin between the first and second body areas. The plural differential pair may include a first pair of fin field effect (FinFET) transistors and a second pair of FinFET transistors. The plural differential pair may include first and second top fin areas projecting from respective portions of a top side of the first and second body areas of the fin. The first and second top fin areas may each have a width that is wider than the first and second body areas of the fin.

    摘要翻译： 多个差分对可以包括具有第一和第二漏极区域的第一半导体鳍片。 第一和第二主体区域可以设置在第一和第二排水区域之间的翅片上。 源区域可以设置在第一和第二身体区域之间的翅片上。 多个差分对可以包括第一对鳍场效应（FinFET）晶体管和第二对FinFET晶体管。 多个差分对可以包括从翅片的第一和第二主体区域的顶侧的相应部分突出的第一和第二顶部翅片区域。 第一和第二顶鳍区域可以各自具有比翅片的第一和第二身体区域宽的宽度。

    Non volatile memory RAD-hard (NVM-rh) system
    34.
    发明授权
    Non volatile memory RAD-hard (NVM-rh) system 失效
    非易失性存储器RAD-hard（NVM-rh）系统

    公开(公告)号：US07551470B2

    公开(公告)日：2009-06-23

    申请号：US11550918

    申请日：2006-10-19

    申请人： Karl R. Erickson ,  John A. Fifield ,  Chandrasekara Kothandaraman ,  Phil C. Paone ,  William R. Tonti

    发明人： Karl R. Erickson ,  John A. Fifield ,  Chandrasekara Kothandaraman ,  Phil C. Paone ,  William R. Tonti

    IPC分类号： G11C17/00

    CPC分类号： G11C17/18 ,  G11C5/005

    摘要： The embodiments of the invention provide an apparatus, method, etc. for a non volatile memory RAD-hard (NVM-rh) system. More specifically, an IC permanent non-volatile storage element comprises an integrated semiconductor stable reference component, wherein the component is resistant to external radiation. The storage element further comprises e-fuse structures in the component and a sensing circuit coupled to the e-fuse structures. The sensing circuit is adapted to update an external device at a specified time interval to reduce incidence of soft errors and errors due to power failure. Moreover, the sensing circuit is adapted to cease updating the external device to program the e-fuse structures; and, continue updating the external device after programming the e-fuse structures.

    摘要翻译： 本发明的实施例提供了一种用于非易失性存储器RAD-hard（NVM-rh）系统的装置，方法等。 更具体地，IC永久性非易失性存储元件包括集成半导体稳定参考元件，其中该元件对外部辐射具有耐受性。 存储元件还包括组件中的e熔丝结构和耦合到电熔丝结构的感测电路。 感测电路适于以特定的时间间隔更新外部设备，以减少由于电源故障引起的软错误和错误的发生。 此外，感测电路适于停止更新外部设备以编程电熔丝结构; 并且在编程电熔丝结构之后继续更新外部设备。

    Non Volatile Memory RAD-hard (NVM-rh) System
    37.
    发明申请
    Non Volatile Memory RAD-hard (NVM-rh) System 失效
    非易失性存储器RAD-hard（NVM-rh）系统

    公开(公告)号：US20080094896A1

    公开(公告)日：2008-04-24

    申请号：US11550918

    申请日：2006-10-19

    申请人： Karl R. Erickson ,  John A. Fifield ,  Chandrasekara Kothandaraman ,  Phil C. Paone ,  William R. Tonti

    发明人： Karl R. Erickson ,  John A. Fifield ,  Chandrasekara Kothandaraman ,  Phil C. Paone ,  William R. Tonti

    IPC分类号： G11C17/00 ,  G11C16/06 ,  G11C11/34 ,  G11C16/04

    CPC分类号： G11C17/18 ,  G11C5/005

    摘要： The embodiments of the invention provide an apparatus, method, etc. for a non volatile memory RAD-hard (NVM-rh) system. More specifically, an IC permanent non-volatile storage element comprises an integrated semiconductor stable reference component, wherein the component is resistant to external radiation. The storage element further comprises e-fuse structures in the component and a sensing circuit coupled to the e-fuse structures. The sensing circuit is adapted to update an external device at a specified time interval to reduce incidence of soft errors and errors due to power failure. Moreover, the sensing circuit is adapted to cease updating the external device to program the e-fuse structures; and, continue updating the external device after programming the e-fuse structures.

    摘要翻译： 本发明的实施例提供了一种用于非易失性存储器RAD-hard（NVM-rh）系统的装置，方法等。 更具体地，IC永久性非易失性存储元件包括集成半导体稳定参考元件，其中该元件对外部辐射具有耐受性。 存储元件还包括组件中的e熔丝结构和耦合到电熔丝结构的感测电路。 感测电路适于以特定的时间间隔更新外部设备，以减少由于电源故障引起的软错误和错误的发生。 此外，感测电路适于停止更新外部设备以编程电熔丝结构; 并且在编程电熔丝结构之后继续更新外部设备。

    Electrically Programmable Fuse Sense Circuit
    40.
    发明申请
    Electrically Programmable Fuse Sense Circuit 失效
    电子可编程保险丝感应电路

    公开(公告)号：US20080157851A1

    公开(公告)日：2008-07-03

    申请号：US11872873

    申请日：2007-10-16

    申请人： Anthony Gus Aipperspach ,  David Howard Allen ,  Phil C. Paone ,  David Edward Schmitt ,  Gregory John Uhlmann

    发明人： Anthony Gus Aipperspach ,  David Howard Allen ,  Phil C. Paone ,  David Edward Schmitt ,  Gregory John Uhlmann

    IPC分类号： H01H37/76 ,  G11C17/16

    CPC分类号： G11C17/18 ,  G11C17/16 ,  H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A design structure for electrically programmable fuse sense circuit having an electrically programmable fuse and a reference resistance. A first current source is coupled, through a first switch, to the electrically programmable fuse. A second current source is coupled, through a second switch, to the reference resistance. A precharge signal enables the first current source, the second current source and closes the first switch and the second switch, creating voltage drops across the electrically programmable fuse and the reference resistance. When the precharge signal goes inactive, the first current source and the second current source are shut off, and, at the same time the first switch and the second switch are opened. A latching circuit uses a difference in the voltage drops when the precharge signal goes inactive to store a state of the electrically programmable fuse, indicative of whether the electrically programmable fuse is blown or unblown.

    摘要翻译： 一种用于电可编程熔丝检测电路的设计结构，其具有电可编程熔丝和参考电阻。 第一电流源通过第一开关耦合到电可编程保险丝。 第二电流源通过第二开关耦合到参考电阻。 预充电信号使得第一电流源，第二电流源能够闭合第一开关和第二开关，从而在电可编程保险丝和参考电阻之间产生电压降。 当预充电信号不起作用时，第一电流源和第二电流源被切断，并且同时第一开关和第二开关断开。 当预充电信号无效以存储电可编程熔丝的状态时，锁存电路使用电压降的差异，指示电可编程熔丝是否被吹制或未被吹出。