公开(公告)号：US20090238181A1

公开(公告)日：2009-09-24

申请号：US12477124

申请日：2009-06-02

申请人： Sachin Desai ,  Tim Millet ,  Zahid Hussain ,  Paul Kim ,  Louise Yeung ,  Ken Yeung

发明人： Sachin Desai ,  Tim Millet ,  Zahid Hussain ,  Paul Kim ,  Louise Yeung ,  Ken Yeung

IPC分类号： H04L12/56

CPC分类号： H04L47/22 ,  H04L12/4625 ,  H04L47/10 ,  H04L47/2441 ,  H04L47/2491 ,  H04L49/254 ,  H04L49/30 ,  H04L49/65

摘要： Methods and systems are provided for steering network packets. According to one embodiment a method is provided for steering incoming network packets. Each network packet processing resource of a network routing/switching device is dynamically assigned to one or more network interfaces of the network routing/switching device. Each of the network packet processing resources includes one or more processing elements and a memory. Incoming network packets received by the network interfaces are steered to an appropriate network packet processing resource based on the dynamic assignment.

摘要翻译： 提供了用于转向网络数据包的方法和系统。 根据一个实施例，提供了一种用于控制传入网络分组的方法。 网络路由/交换设备的每个网络分组处理资源被动态分配给网络路由/交换设备的一个或多个网络接口。 每个网络分组处理资源包括一个或多个处理元件和存储器。 基于动态分配，由网络接口​​接收的传入网络分组被引导到适当的网络分组处理资源。

公开(公告)号：US20080095237A1

公开(公告)日：2008-04-24

申请号：US11763779

申请日：2007-06-15

申请人： Zahid Hussain ,  John Brothers ,  Jim Xu

发明人： Zahid Hussain ,  John Brothers ,  Jim Xu

IPC分类号： H04N5/00

CPC分类号： G06T15/04 ,  G06T7/238 ,  G06T2200/28 ,  G06T2207/10016 ,  G06T2207/20052 ,  H04N19/43 ,  H04N19/523 ,  H04N19/533 ,  H04N19/56 ,  H04N19/61

摘要： Disclosed is a graphics processing unit comprising an instruction decoder and sum-of-absolute-differences (SAD) accleration logic. The instruction decoder is configured to decode a SAD instruction into parameters describing an M×N and an n×n pixel block in U,V coordinates. The SAD accleration logic is configured to receive the parameters and compute SAD scores. Each SAD score corresponds to the n×n block and to one block contained within the M×N pixel block and horizontally offset within the n×n block. Also disclosed is a GPU comprising a host processor interface receiving video acceleration instructions and a video acceleration unit. The unit is responsive to the instructions and comprises SAD accleration logic configured to receive the parameters and compute SAD scores. Each SAD score corresponds to an n×n pixel block and to one block contained within an M×N block and horizontally offset within the n×n block. M, N, and n are integers.

摘要翻译： 公开了一种图形处理单元，包括指令解码器和绝对差值（SAD）积分逻辑。 指令解码器被配置为将SAD指令解码成描述U，V坐标中的MxN和nxn像素块的参数。 SAD加密逻辑被配置为接收参数并计算SAD分数。 每个SAD分数对应于nxn块和包含在M×N像素块内的一个块，并且在n×n块内水平偏移。 还公开了一种GPU，其包括接收视频加速指令的主处理器接口和视频加速单元。 该单元响应于指令，并包括配置为接收参数并计算SAD分数的SAD加速逻辑。 每个SAD分数对应于n×n像素块，并对应于包含在M×N块内的一个块，并且在n×n块内水平偏移。 M，N和n是整数。

公开(公告)号：US20070294329A1

公开(公告)日：2007-12-20

申请号：US11763729

申请日：2007-06-15

申请人： Zahid Hussain

发明人： Zahid Hussain

IPC分类号： G06F17/10

CPC分类号： H04N19/86 ,  H04N19/12 ,  H04N19/122 ,  H04N19/136 ,  H04N19/176 ,  H04N19/423 ,  H04N19/61 ,  H04N19/82

摘要： Included are embodiments for processing video data. At least one embodiment includes receive logic configured to receive the video data chosen from a plurality of formats and filter logic configured to filter the video data according to the instruction. Similarly, some embodiments include transform logic configured to transform the video data according to the instruction, where the instruction contains a mode indication in which the filter logic and the transform logic execute based on the format of the video data.

摘要翻译： 包括用于处理视频数据的实施例。 至少一个实施例包括被配置为接收从多个格式中选择的视频数据的接收逻辑和被配置为根据指令过滤视频数据的滤波器逻辑。 类似地，一些实施例包括被配置为根据指令变换视频数据的变换逻辑，其中指令包含基于视频数据的格式来执行滤波器逻辑和变换逻辑的模式指示。

公开(公告)号：US07310100B2

公开(公告)日：2007-12-18

申请号：US10879325

申请日：2004-06-29

申请人： Zahid Hussain

发明人： Zahid Hussain

IPC分类号： G09G5/36 ,  G06T11/40 ,  G06T15/40 ,  G06T1/20

CPC分类号： G06T1/20

摘要： An efficient graphics pipeline with a pixel cache and data pre-fetching. By combining the use of a pixel cache in the graphics pipeline and the pre-fetching of data into the pixel cache, the graphics pipeline of the present invention is able to take best advantage of the high bandwidth of the memory system while effectively masking the latency of the memory system. More particularly, advantageous reuse of pixel data is enabled by caching, which when combined with pre-fetching masks the memory latency and delivers high throughput. As such, the present invention provides a novel and superior graphics pipeline over the prior art in terms of more efficient data access and much greater throughput. In one embodiment, the present invention is practiced within a computer system having a processor for issuing commands; a memory sub-system for storing information including graphics data; and a graphics sub-system for processing the graphics data according to the commands from the processor. The graphics sub-system comprises a rasterizer for traversing graphics primitives of the graphics data to generate pixel coordinates for pixels corresponding to the graphics primitives; a graphics pipeline for processing the graphics data of the pixels; and a pixel cache for caching the pixel data. In this embodiment, he graphics sub-system masks the inherent latency of the memory sub-system by pre-fetching the graphics data and storing the graphics data within the pixel cache.

摘要翻译： 具有像素缓存和数据预取功能的高效图形流水线。 通过结合使用图形流水线中的像素高速缓存和将数据预取入像素高速缓存，本发明的图形流水线能够最大限度地利用存储器系统的高带宽，同时有效地掩盖等待时间 的内存系统。 更具体地，通过高速缓存来实现像素数据的有利重用，其通过与预取掩码相结合来存储存储器等待时间并提供高吞吐量。 因此，就更有效的数据访问和更大的吞吐量而言，本发明提供了一种比现有技术更新和优越的图形流水线。 在一个实施例中，本发明在具有用于发出命令的处理器的计算机系统内实现; 用于存储包括图形数据的信息的存储器子系统; 以及用于根据来自处理器的命令处理图形数据的图形子系统。 图形子系统包括用于遍历图形数据的图形基元的光栅化器，以生成与图形基元对应的像素的像素坐标; 用于处理像素的图形数据的图形管线; 以及用于缓存像素数据的像素缓存。 在该实施例中，他的图形子系统通过预取图形数据并将图形数据存储在像素高速缓存中来掩蔽存储器子系统的固有延迟。

公开(公告)号：US20070061389A1

公开(公告)日：2007-03-15

申请号：US11223289

申请日：2005-09-09

申请人： Zahid Hussain

发明人： Zahid Hussain

IPC分类号： G06F1/02

CPC分类号： G06F1/0307 ,  G06F7/556

摘要： Embodiments of logarithm processing systems and methods are disclosed. The system embodiments described herein comprise two tables corresponding to various base and derivative functions of a logarithm, with logic configured to access the tables and format and normalize the accessed values to evaluate the logarithm using a standard FMAD unit.

摘要翻译： 公开了对数处理系统和方法的实施例。 本文描述的系统实施例包括对应于对数的各种基本和导数函数的两个表，其中逻辑被配置为访问表格并格式化和归一化所访问的值以使用标准FMAD单元来评估对数。

公开(公告)号：US20160376272A1

公开(公告)日：2016-12-29

申请号：US15116547

申请日：2015-02-06

申请人： Santhosh F. NEELAKAVIL ,  Scott D. EDMONDSON ,  Alan W. HRUZA ,  Zahid HUSSAIN ,  Charles LESBURG ,  Remond MONINGKA ,  Merck Sharp & Dohme Corp.

发明人： Santhosh F. Neelamkavil ,  Scott D. Edmondson ,  Alan W. Hruza ,  Zahid Hussain ,  Charles Lesburg ,  Remond Moningka

IPC分类号： C07D471/08 ,  C07D487/08

CPC分类号： C07D471/08 ,  C07D487/08

摘要： The present invention provides a compound of Formula (I) and pharmaceutical compositions comprising one or more said compounds, and methods for using said compounds for treating or preventing thromboses, embolisms, hypercoagulability or fibrotic changes. The compounds are selective Factor XIa inhibitors or dual inhibitors of Factor XIa and plasma kallikrein.

公开(公告)号：US09525905B2

公开(公告)日：2016-12-20

申请号：US13325964

申请日：2011-12-14

申请人： Zahid Hussain

发明人： Zahid Hussain

IPC分类号： G09G5/00 ,  H04N21/422 ,  H04N21/431 ,  H04N21/443

CPC分类号： H04N21/42207 ,  H04N21/42209 ,  H04N21/4222 ,  H04N21/42224 ,  H04N21/4312 ,  H04N21/4431

摘要： A content player transmits a screen image to a display. The screen image includes an active region, which may be a portion that may be manipulated. The player determines active region information for the active region and transmits such to a portable device. The portable device receives the active region information as well as information regarding any inactive regions, which may be portions that may not be manipulated. The portable device utilizes the information to present a simulated version of the screen image on a touch screen. The portable device may then receive manipulation information via the touch screen and transmit such to the player. In response, the player may generate and present an updated version of the screen image, determine updated information, and transmit such to the portable device. The portable device may utilize the updated information to present a simulated updated version of the screen image.

摘要翻译： 内容播放器将屏幕图像发送到显示器。 屏幕图像包括有效区域，其可以是可以被操纵的部分。 播放器确定活动区域的有效区域信息并将其发送到便携式设备。 便携式设备接收有源区域信息以及关于任何不活动区域的信息，其可以是可能不被操纵的部分。 便携式设备利用该信息在触摸屏上呈现屏幕图像的模拟版本。 便携式设备然后可以经由触摸屏接收操作信息并将其发送给播放器。 作为响应，播放器可以生成并呈现屏幕图像的更新版本，确定更新的信息，并将其发送到便携式设备。 便携式设备可以利用更新的信息来呈现屏幕图像的模拟更新版本。

公开(公告)号：US09319708B2

公开(公告)日：2016-04-19

申请号：US11763797

申请日：2007-06-15

申请人： Zahid Hussain

发明人： Zahid Hussain

IPC分类号： H04N11/02 ,  H04N19/523 ,  H04N19/56 ,  H04N19/43 ,  H04N19/533

CPC分类号： H04N19/523 ,  H04N19/43 ,  H04N19/533 ,  H04N19/56

摘要： The embodiments disclosed herein provide systems and methods for improved motion estimation using a graphics processing unit. One such embodiment includes a method for determining a motion vector describing motion relative to a reference block, which comprises determining which of a plurality of prediction blocks is a good match with the reference block, according to a match criteria. The method further comprises performing a local area exhaustive search, in an area centered around the good match prediction block, to produce a best match with the reference block. The best match has integral pixel resolution. The method further comprises modeling the degree of match between the best match and the reference block as a quadratic surface and analytically determining a minima of the quadratic surface, corresponding to a best matching block with fractional resolution. The method further comprises computing a fractional motion vector based on the best matching block with fractional resolution.

摘要翻译： 本文公开的实施例提供了使用图形处理单元改进运动估计的系统和方法。 一个这样的实施例包括一种用于确定描述相对于参考块的运动的运动矢量的方法，其包括根据匹配标准确定多个预测块中的哪一个与参考块的良好匹配。 该方法还包括在以好匹配预测块为中心的区域内执行局部区域详尽搜索，以产生与该参考块的最佳匹配。 最佳匹配具有整体像素分辨率。 该方法还包括将最佳匹配和参考块之间的匹配程度建模为二次曲面，并分析确定二次曲面的最小值，对应于具有分数分辨率的最佳匹配块。 该方法还包括基于具有分数分辨率的最佳匹配块计算分数运动矢量。

公开(公告)号：US08848718B2

公开(公告)日：2014-09-30

申请号：US12467609

申请日：2009-05-18

申请人： Zahid Hussain ,  Sachin Desai ,  Naveed Alam ,  Joseph Cheng ,  Tim Millet

发明人： Zahid Hussain ,  Sachin Desai ,  Naveed Alam ,  Joseph Cheng ,  Tim Millet

IPC分类号： H04L12/28 ,  H04L12/66 ,  G06F15/173

CPC分类号： H04L45/60 ,  H04L43/026 ,  H04L43/0829 ,  H04L43/0894 ,  H04L45/586 ,  H04L47/10 ,  H04L47/11

摘要： Methods and systems are provided for applying metering and rate-limiting in a virtual router environment and supporting a hierarchy of metering/rate-limiting contexts per packet flow. According to one embodiment, multiple first level metering options and multiple second level metering options associated with a hierarchy of metering levels are provided. A virtual routing engine receives packets associated with a first packet flow and packets associated with a second packet flow. The virtual routing engine performs a first type of metering of the first level metering options on the packets associated with the first packet flow using a first metering control block (MCB) and performs a second type of metering of the second level metering options on the packets associated with the first packet flow and the packets associated with the second packet flow using a second MCB.

摘要翻译： 提供了方法和系统，用于在虚拟路由器环境中应用计量和速率限制，并支持每个数据包流的计量/速率限制上下文的层次。 根据一个实施例，提供与测量级别的层级相关联的多个第一级计量选项和多个第二级计量选项。 虚拟路由引擎接收与第一分组流相关联的分组以及与第二分组流相关联的分组。 虚拟路由引擎使用第一计量控制块（MCB）执行与第一分组流相关联的分组上的第一级计量选项的第一类型的测量，并且对分组执行第二级计量选项的第二类型的测量 使用第二MCB与第一分组流和与第二分组流相关联的分组相关联。

公开(公告)号：US08064462B2

公开(公告)日：2011-11-22

申请号：US12781808

申请日：2010-05-17

申请人： Zahid Hussain ,  Tim Millet

发明人： Zahid Hussain ,  Tim Millet

IPC分类号： H04L12/28 ,  H04L12/50 ,  H04Q11/00 ,  G06F15/173

CPC分类号： H04L47/2441 ,  H04L45/00 ,  H04L45/20 ,  H04L45/586 ,  H04L45/60 ,  H04L47/10 ,  H04L47/125 ,  H04L47/2408 ,  H04L47/2491 ,  H04L47/326 ,  H04L47/50 ,  H04L47/6215 ,  H04L47/623 ,  H04L49/70 ,  H04L61/2503 ,  H04L61/6004 ,  H04L63/02 ,  H04L63/0236 ,  H04L63/0272 ,  H04L63/0428 ,  H04L63/061 ,  H04L63/062 ,  H04L63/101 ,  H04L63/164 ,  H04L69/22 ,  H04L69/24

摘要： Methods and systems for providing IP services in an integrated fashion are provided. According to one embodiment, a system includes a switch fabric and a line interface/network module, multiple virtual routing engines (VREs) and a virtual services engine (VSE) coupled with the switch fabric. The line interface/network module receives packets, steers ingress packets to a selected VRE and transmits egress packets according to their relative priority. VREs determines if a packet associated with a packet flow requires processing by the VSE by performing flow-based packet classification on the packet and evaluating forwarding state information associated with previously stored flow learning results. The VSE includes a central processing unit configured to perform firewall processing, Uniform Resource Locator (URL) filtering and anti-virus processing. If the packet is determined to require processing by the VSE, then the packet is steered to the VSE for firewall, URL filtering and/or anti-virus processing.

摘要翻译： 提供了以集成方式提供IP服务的方法和系统。 根据一个实施例，系统包括交换结构和线路接口/网络模块，多个虚拟路由引擎（VRE）和与交换结构耦合的虚拟服务引擎（VSE）。 线路接口/网络模块接收分组，将入口分组引导到所选择的VRE，并根据其相对优先级发送出口分组。 VRE确定与分组流相关联的分组是否需要通过在分组上执行基于流的分组分类并且评估与先前存储的流学习结果相关联的转发状态信息来由VSE进行处理。 VSE包括配置为执行防火墙处理，统一资源定位符（URL）过滤和防病毒处理的中央处理单元。 如果分组被确定为需要由VSE进行处理，则该分组被引导到用于防火墙，URL过滤和/或防病毒处理的VSE。