摘要:
A semiconductor memory device can stabilize a voltage level of a normal driving voltage terminal in a normal driving operation, which is performed after an overdriving operation, even when an overdriving voltage is unstable due to environmental factors of the semiconductor memory device in the overdriving operation. The semiconductor memory device includes a bit line sense amplifier for performing an amplification operation using a normal driving voltage or an overdriving voltage to sense and amplify data applied to bit lines, a normal driving voltage compensator configured to drive a normal driving voltage terminal according to a voltage level of the normal driving voltage terminal and target normal driving voltage levels, and a discharge enable signal generator configured to generate a discharge enable signal by adjusting an activation period of the discharge enable signal according to the overdriving voltage.
摘要:
A voltage generating unit of a semiconductor memory device makes it possible to reduce a peak current value when generating a high voltage. The voltage generating unit of the semiconductor memory device includes a detecting unit configured to detect a voltage level of a high voltage by comparing a reference voltage with a fed-back high voltage, an oscillating unit configured to generate a plurality of clock signals with different operation time points on the basis of an output signal of the detecting unit, and a plurality of pumping units configured to generate the high voltage according to pumping control signals based on the clock signals.
摘要:
A semiconductor memory device for sensing voltages of bit lines in high speed includes: a first bit line pair to a fourth bit line pair each coupled to a different unit cell array; a bit line sense amplifying unit coupled to the first bit line pair to the fourth bit line pair for amplifying data transmitted through the first bit line pair to the fourth bit line pair; and a switching block for connecting one of the first bit line pair to the fourth bit line pair with the bit line sense amplifying unit in response to a control signal.
摘要:
An internal voltage generator includes a voltage comparator operating in response to an enable signal, comparing a reference voltage with a feedback voltage and outputting a comparison signal through a first node. A driving controller outputs a drive control signal in response to the comparison signal. An output driver outputs an internal voltage through a second node in response to the drive control signal. An initial operation stabilizer controls the driving controller for a certain period at which the enable signal is enabled to block an output of the drive control signal.
摘要:
An internal voltage generating circuit of a semiconductor memory apparatus includes a first voltage generating unit to output a first output voltage to a common node, the first output voltage is generated in response to a first reference voltage, and a second voltage generating unit to output a second output voltage to the common node, the second output voltage is generated in response to a second reference voltage.
摘要:
A reference voltage supplying circuit can include an internal reference voltage generating unit configured to generate an internal reference voltage, a pad configured to receive an external reference voltage, a switching unit selectively configured to supply the internal reference voltage or the external reference voltage to an internal voltage generator in a test mode.
摘要:
A reference voltage supplying circuit can include an internal reference voltage generating unit configured to generate an internal reference voltage, a pad configured to receive an external reference voltage, a switching unit selectively configured to supply the internal reference voltage or the external reference voltage to an internal voltage generator in a test mode.
摘要:
Semiconductor memory device and method of operating the same includes an enable signal generator configured to generate first and second enable signals having activation timings determined in response to activation of an active command, the first enable signal being deactivated after a first time from a deactivation timing of the active command, and the second enable signal being deactivated after a second time longer than the first time from the deactivation timing of the active command. Internal voltage generators are configured to generate internal voltages. At least one of the internal voltage generators is turned on/off in response to the first enable signal, and at least one other of the internal voltage generators is turned on/off in response to the second enable signals.
摘要:
A semiconductor memory device includes a voltage detector configured to detect a level of an external power supply voltage and an internal voltage generator configured to generate an internal voltage in response to an active signal and drive an internal voltage terminal with a driving ability corresponding to an output signal of the voltage detector. A method for operating the semiconductor memory device includes detecting a level of an external power supply voltage, based on a first target level, to output a detection signal; and generating an internal voltage in response to an active signal, and driving an internal voltage terminal with a driving ability corresponding to the detection signal.
摘要:
A semiconductor device includes a common probing pad; an internal voltage generation unit having a plurality of internal voltage generation blocks configured to generate a plurality of internal voltages; and a probing voltage selection unit configured to transfer an internal voltage selected from the internal voltages to the common probing pad in response to a plurality of voltage selection signals.