公开(公告)号：US07580293B2

公开(公告)日：2009-08-25

申请号：US11700186

申请日：2007-01-31

申请人： Kohji Kanamori ,  Kenichi Kuboyama

发明人： Kohji Kanamori ,  Kenichi Kuboyama

IPC分类号： G11C16/04

CPC分类号： H01L27/115 ,  G11C16/10

摘要： A programmable non-volatile semiconductor memory device includes a select gate 3, arranged in a first region on a substrate, a floating gate 6 arranged in a second region neighboring to the first region, a first diffusion region 7 provided in a third region neighboring to the second region, a control gate 11 arranged on the floating gate 6, and a driving circuit 22 adapted for controlling voltages applied to the substrate 1 (well 1a), select gate 3, first diffusion region 7 and control gate 11. The driving circuit performs control so that, during erasure operation, voltages applied to select gate 3 and the control gate 11 are negative, with the remaining voltage, applied to the substrate 1 (or well 1a), being positive. The device permits erasure operation at a lower voltage.

摘要翻译： 可编程非易失性半导体存储器件包括：布置在衬底上的第一区域中的选择栅极3，布置在与第一区域相邻的第二区域中的浮置栅极6，设置在与第一区域相邻的第三区域中的第一扩散区域7 第二区域，布置在浮置栅极6上的控制栅极11和适于控制施加到基板1（阱1a），选择栅极3，第一扩散区域7和控制栅极11的电压的驱动电路22。 执行控制，使得在擦除操作期间，施加到选择栅极3和控制栅极11的电压为负，而施加到衬底1（或阱1a）的剩余电压为正。 该器件允许在较低电压下的擦除操作。

公开(公告)号：US07268385B2

公开(公告)日：2007-09-11

申请号：US10892553

申请日：2004-07-16

申请人： Teiichirou Nishizaka ,  Kohji Kanamori

发明人： Teiichirou Nishizaka ,  Kohji Kanamori

IPC分类号： H01L29/788

CPC分类号： H01L27/11568 ,  G11C16/0458 ,  G11C16/0491 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11546 ,  H01L29/7923

摘要： A semiconductor memory device comprises diffusion regions, a floating gate, a third diffusion region, a selection gate electrode, and a control gate electrode that three-dimensionally crosses the selection gate electrode and extends in a direction orthogonal to the selection gate electrode are included. A channel formed immediately below the selection gate and which constitutes a passage connecting the two diffusion regions has a shape in a top view, including a first path extending in one direction, from one diffusion region, and a second path extending from the end of the first path to the other diffusion region in a direction orthogonal to a first direction.

摘要翻译： 包括半导体存储器件，其包括扩散区域，浮置栅极，第三扩散区域，选择栅极电极和三维地穿过选择栅电极并沿与选择栅电极正交的方向延伸的控制栅电极。 形成在选择栅极正下方的通道，其构成连接两个扩散区域的通道，具有从一个扩散区域向一个扩散区域延伸的包括从一个方向延伸的第一路径和从第二路径延伸的第二路径的俯视图形状 在与第一方向正交的方向上的另一扩散区的第一路径。

公开(公告)号：US20070189077A1

公开(公告)日：2007-08-16

申请号：US11704934

申请日：2007-02-12

申请人： Kohji Kanamori

发明人： Kohji Kanamori

IPC分类号： G11C16/04 ,  G11C11/34 ,  G11C16/06

CPC分类号： H01L27/115 ,  G11C16/10 ,  H01L27/11521

摘要： A programmable non-volatile semiconductor memory device having which a sufficient operational margin with miniaturized memory cells. The memory device includes select gates 3, arranged in a first region on a substrate 1, floating gates 6, arranged in a second region, neighboring to the first region, first diffusion regions 7, arranged in a third region neighboring to the second region, and control gates 11 arranged above the floating gates 6. It also includes a driving circuit 22 for controlling the voltages applied to the substrate 1, select gates 3, first diffusion areas 7 and the controlling gates 11. At the time of reprogramming, the driving circuit 22 controls the voltages for first control and second control. The first control sets a low threshold voltage state, inclusive of the depletion state, for the bits, connected to a selected one of the control gates 11. The second control sets a low threshold voltage state or a high threshold voltage state of a desired enhancement state from one bit to another.

摘要翻译： 一种可编程的非易失性半导体存储器件，具有足够的操作余量与小型化的存储器单元。 存储装置包括选择栅极3，布置在基板1上的第一区域中，布置在与第一区域相邻的第二区域中的浮置栅极6布置在与第二区域相邻的第三区域中的第一扩散区域7， 以及布置在浮置栅极6上方的控制栅极11.它还包括用于控制施加到基板1，选择栅极3，第一扩散区域7和控制栅极11的电压的驱动电路22.在重新编程时，驱动 电路22控制用于第一控制和第二控制的电压。 第一控制器对连接到所选择的一个控制门11的位设置包括耗尽状态的低阈值电压状态。第二控制设置低阈值电压状态或期望增强的高阈值电压状态 状态从一点到另一位。

公开(公告)号：US20070183212A1

公开(公告)日：2007-08-09

申请号：US11700184

申请日：2007-01-31

申请人： Kohji Kanamori

发明人： Kohji Kanamori

IPC分类号： G11C11/34 ,  G11C16/06

CPC分类号： H01L27/11524 ,  G11C16/10 ,  H01L27/115 ,  H01L27/11521

摘要： A drive circuit 22 controls voltages applied to a substrate 1, selection gates SG0 and SG1, a local bit line LB2, and a control gate CGn. By respectively applying a negative voltage to the control gate CGn, a positive voltage to the selection gate SG0, a voltage lower than the voltage applied to the selection gate SG0 to the selection gate SG1, and a positive voltage to the local bit line LB2, the drive circuit 22 controls so that electrons are selectively drawn out of a floating gate FG3 to the local bit line LB2 by F-N tunneling during writing operation. Sufficient operation margin is obtained even when memory cells are miniaturized.

摘要翻译： 驱动电路22控制施加到基板1，选择栅极SG0和SG1，局部位线LB2和控制栅极CGn的电压。 通过分别对控制栅极CGn施加负电压，向选择栅极SG0施加正电压，低于施加到选择栅极SG0的电压至选择栅极SG1的电压，以及对该局部位置的正电压 线路LB2，驱动电路22进行控制，使得在写入操作期间，通过FN隧穿，电子被选择性地从浮动栅极FG3拉出到局部位线LB 2。 即使存储单元小型化，也能获得足够的操作余量。

公开(公告)号：US20060261400A1

公开(公告)日：2006-11-23

申请号：US11431569

申请日：2006-05-11

申请人： Naoaki Sudo ,  Kohji Kanamori

发明人： Naoaki Sudo ,  Kohji Kanamori

IPC分类号： H01L29/788

CPC分类号： H01L29/7887 ,  H01L27/0207 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524

摘要： A nonvolatile semiconductor storage device in which one unit cell comprises a select gate 3 (3a-3i) provided in a first region on a substrate 1; a floating gate 6 provided in a second region adjacent to the first region; a diffused region 7b adjacent to the second region and provided in a third region on the surface of the substrate 1; and a control gate 11 provided on the floating gate 6. The select gate 3 is divided into three or more in an erase block 23 composed of all unit cells, from each of which electrons are extracted from the floating gate, at the same time when an erase operation is performed. Each of the select gates 3a-3i, created by the division, is formed in a comb-like shape in which, when viewed from the direction of a normal line to a plane, a plurality of comb teeth extend from a common line. The comb teeth of a select gate (for example, 3b) are arranged in gaps between the comb teeth of an adjacent select gate (for example, 3a, 3c) at a predetermined spacing.

摘要翻译： 一种非易失性半导体存储装置，其中一个单位单元包括设置在基板1上的第一区域中的选择栅极3（3 a-3 i） 设置在与第一区域相邻的第二区域中的浮动栅极6; 与第二区域相邻并设置在基板1的表面的第三区域中的扩散区域7b; 以及设置在浮置栅极6上的控制栅极11.选择栅极3在由所有单位单元构成的擦除块23中被划分为三个或更多个，其中每一个从浮置栅极中提取电子，同时当 执行擦除操作。 通过划分产生的选择门3a-3i中的每一个形成为梳状形状，其中从法线到平面的方向观察时，多个梳齿从公共线 。 选择门（例如，3b）的梳齿布置在相邻选择栅极的梳齿之间的间隙（例如，3a，3c）中，以预定间隔布置。

公开(公告)号：US06436769B1

公开(公告)日：2002-08-20

申请号：US10029275

申请日：2001-12-28

申请人： Kohji Kanamori

发明人： Kohji Kanamori

IPC分类号： H01L218247

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/7885 ,  Y10S438/919

摘要： The present invention provides a flash memory having a split gate structure and virtual ground array structure, wherein a high impurity concentration region of a first conductivity type is provided in a drain adjacent region of a channel region under a floating gate electrode, and the high impurity concentration region has a highest impurity concentration in the channel region, and wherein a low impurity concentration region of a first conductivity type is provided in the channel region but at a part not covered by the floating gate.

摘要翻译： 本发明提供了一种具有分离栅极结构和虚拟接地阵列结构的闪速存储器，其中第一导电类型的高杂质浓度区域设置在浮置栅电极下方的沟道区域的漏极相邻区域中，并且高杂质 浓度区域在沟道区域中具有最高的杂质浓度，并且其中在沟道区域中提供第一导电类型的低杂质浓度区域，但是在未被浮置栅极覆盖的部分。

公开(公告)号：US6165847A

公开(公告)日：2000-12-26

申请号：US289192

申请日：1999-04-09

申请人： Kohji Kanamori

发明人： Kohji Kanamori

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11521 ,  H01L27/115 ,  Y10S438/919

摘要： A nonvolatile semiconductor memory device having a semiconductor substrate of a first conductive type, a floating gate and a control gate provided on the semiconductor substrate, at least a pair of impurity diffusion layers of a second conductive type defining source and drain and disposed in the semiconductor substrate in a spaced relation to each other so as to define a channel having a region covered with the floating gate and a region uncovered with the floating gate, the region uncovered with the floating gate defining a split gate, a first impurity diffusion layer region formed in the semiconductor substrate so as to be disposed at least at an area between the pair of diffusion layers, and a second impurity diffusion layer region having an impurity concentration lower than the first impurity diffusion layer region and formed in the semiconductor substrate so as to be disposed at the split gate.

摘要翻译： 一种非易失性半导体存储器件，具有设置在半导体衬底上的第一导电类型，浮置栅极和控制栅极的半导体衬底，至少一对限定源极和漏极的第二导电类型的杂质扩散层，并设置在半导体 衬底彼此间隔开的关系，以便限定具有被浮置栅极覆盖的区域的通道和未被浮动栅极覆盖的区域，所述浮动栅极未覆盖的区域限定分离栅极，形成第一杂质扩散层区域 在所述半导体衬底中至少设置在所述一对扩散层之间的区域，以及第二杂质扩散层区域，所述第二杂质扩散层区域的杂质浓度低于所述第一杂质扩散层区域，并形成在所述半导体衬底中， 设在分裂门。

公开(公告)号：US08008705B2

公开(公告)日：2011-08-30

申请号：US11194561

申请日：2005-08-02

申请人： Kohji Kanamori

发明人： Kohji Kanamori

IPC分类号： H01L29/788

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42328

摘要： Disclosed is a semiconductor storage device having a trench around a bit-line diffusion region in an area of a p-well, which constitutes a memory cell area, that is not covered by a word line and a select gate that intersects the word line. An insulating film is buried in the trench.

摘要翻译： 公开了一种半导体存储装置，其在p阱的区域中具有围绕位线扩散区域的沟槽，构成未被字线覆盖的存储单元区域和与字线相交的选择栅极。 绝缘膜被埋在沟槽中。

公开(公告)号：US20070183222A1

公开(公告)日：2007-08-09

申请号：US11700186

申请日：2007-01-31

申请人： Kohji Kanamori ,  Kenichi Kuboyama

发明人： Kohji Kanamori ,  Kenichi Kuboyama

IPC分类号： G11C16/04 ,  G11C11/34

CPC分类号： H01L27/115 ,  G11C16/10

摘要： A programmable non-volatile semiconductor memory device includes a select gate 3, arranged in a first region on a substrate, a floating gate 6 arranged in a second region neighboring to the first region, a first diffusion region 7 provided in a third region neighboring to the second region, a control gate 11 arranged on the floating gate 6, and a driving circuit 22 adapted for controlling voltages applied to the substrate 1 (well 1a), select gate 3, first diffusion region 7 and control gate 11. The driving circuit performs control so that, during erasure operation, voltages applied to select gate 3 and the control gate 11 are negative, with the remaining voltage, applied to the substrate 1 (or well 1a), being positive. The device permits erasure operation at a lower voltage.

摘要翻译： 可编程非易失性半导体存储器件包括：布置在衬底上的第一区域中的选择栅极3，布置在与第一区域相邻的第二区域中的浮置栅极6，设置在与第一区域相邻的第三区域中的第一扩散区域7 第二区域，布置在浮置栅极6上的控制栅极11和适于控制施加到基板1（阱1a），选择栅极3，第一扩散区域7和控制栅极11的电压的驱动电路22。 电路进行控制，使得在擦除操作期间，施加到选择栅极3和控制栅极11的电压为负，而施加到衬底1（或阱1a）的剩余电压为正。 该器件允许在较低电压下的擦除操作。

公开(公告)号：US20070045715A1

公开(公告)日：2007-03-01

申请号：US11510618

申请日：2006-08-28

申请人： Naoaki Sudo ,  Kohji Kanamori ,  Kazuhiko Sanada

发明人： Naoaki Sudo ,  Kohji Kanamori ,  Kazuhiko Sanada

IPC分类号： H01L29/788

CPC分类号： H01L29/7885 ,  G11C16/0491 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42324

摘要： A semiconductor storage device in which product cost is reduced includes a memory cell section (cells belonging to word lines) and a bypass section (cells belonging to bypass word lines). The memory cell section has a select gate, floating gates, a first diffusion region, a second diffusion region and a first control gate. The bypass section has the first select gate, the first diffusion region, the second diffusion region and a second control gate. The second control gate controls a channel in an area between the select gate and the first diffusion region or between the select gate and the second diffusion region. The channel of the bypass section becomes a current supply path when a cell of the memory cell section is read out.

摘要翻译： 产品成本降低的半导体存储装置包括存储单元部分（属于字线的单元）和旁路部分（属于旁路字线的单元）。 存储单元部分具有选择栅极，浮置栅极，第一扩散区域，第二扩散区域和第一控制栅极。 旁路部分具有第一选择栅极，第一扩散区域，第二扩散区域和第二控制栅极。 第二控制栅极控制选择栅极和第一扩散区域之间或选择栅极和第二扩散区域之间的区域中的沟道。 当读出存储单元部分的单元时，旁通部分的通道变为电流供应路径。