Process for damascene structure with reduced low-k damage
    31.
    发明授权
    Process for damascene structure with reduced low-k damage 有权
    具有降低低k损伤的镶嵌结构的工艺

    公开(公告)号:US08951911B2

    公开(公告)日:2015-02-10

    申请号:US13174621

    申请日:2011-06-30

    摘要: Embodiments described herein generally provide methods for reducing undesired low-k damages during a damascene process using a sacrificial dielectric material and optionally a barrier/capping layer. In one embodiment, a damascene structure is formed through a sacrificial dielectric material deposited over a dielectric base layer. The damascene structure is filled with a suitable metal such as copper. The sacrificial dielectric material filled in trench areas between the copper damascene is then removed, followed by a barrier/cap layer which conformally or selectively covers exposed surfaces of the copper damascene structure. Ultra low-k dielectric materials may then fill the trench areas that were previously filled with sacrificial dielectric material. The invention prevents the ultra low-k material between the metal lines from exposing to various damaging processes during a damascene process such as etching, stripping, wet cleaning, pre-metal cleaning or CMP process.

    摘要翻译: 本文描述的实施例通常提供用于在使用牺牲介电材料和任选的阻挡/覆盖层的镶嵌工艺期间减少不希望的低k损伤的方法。 在一个实施例中,通过沉积在电介质基底层上的牺牲绝缘材料形成镶嵌结构。 镶嵌结构填充有合适的金属如铜。 填充在铜镶嵌之间的沟槽区域中的牺牲介电材料然后被去除,随后是保形或选择性地覆盖铜镶嵌结构的暴露表面的阻挡层/盖层。 然后,超低k电介质材料可以填充先前填充有牺牲介电材料的沟槽区域。 本发明防止金属线之间的超低k材料在蚀刻,剥离,湿法清洗,金属前清洗或CMP工艺的大马士革处理过程中暴露于各种破坏性工艺。

    POST-ASH SIDEWALL HEALING
    32.
    发明申请
    POST-ASH SIDEWALL HEALING 审中-公开
    后腰围护理

    公开(公告)号:US20120009796A1

    公开(公告)日:2012-01-12

    申请号:US12909167

    申请日:2010-10-21

    IPC分类号: H01L21/3065

    摘要: Methods of decreasing the effective dielectric constant present between two conducting components of an integrated circuit are described. The methods involve the use of a gas phase etch which is selective towards the oxygen-rich portion of the low-K dielectric layer. The etch rate attenuates as the etch process passes through the relatively high-K oxygen-rich portion and reaches the low-K portion. The etch process may be easily timed since the gas phase etch process does not readily remove the desirable low-K portion.

    摘要翻译: 描述了降低集成电路的两个导电部件之间存在的有效介电常数的方法。 该方法包括使用对低K电介质层的富氧部分具有选择性的气相蚀刻。 当蚀刻工艺通过较高K富氧部分并达到低K部分时,蚀刻速率衰减。 由于气相蚀刻工艺不容易除去所需的低K部分,所以蚀刻工艺可以容易地定时。