公开(公告)号：US09214351B2

公开(公告)日：2015-12-15

申请号：US13970482

申请日：2013-08-19

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yi-Hsuan Hsiao ,  Hang-Ting Lue ,  Wei-Chen Chen

IPC: G11C16/04 ,  H01L21/28 ,  H01L29/792 ,  H01L27/115 ,  G11C16/34 ,  G11C16/10 ,  G11C16/26

CPC classification number: G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C16/3418 ,  H01L21/28282 ,  H01L27/11578 ,  H01L29/7926

Abstract: A 3D memory device includes an improved dual gate memory cell. The improved dual gate memory cell has a channel body with opposing first and second side surfaces, charge storage structures on the first and second side surfaces, and a gate structure overlying the charge storage structures on both the first and second side surfaces. The channel body has a depth between the first and second side surfaces less than a threshold channel body depth, combined with the gate structure which establishes an effective channel length of the cell greater than a threshold length. The combination of the channel body depth and effective channel length are related so that the cell channel body can be fully depleted, and sub-threshold leakage current can be suppressed when the memory cell has a high threshold state under a read bias.

Abstract translation: 3D存储器件包括改进的双栅极存储单元。 改进的双栅极存储单元具有通道体，其具有相对的第一和第二侧表面，第一和第二侧表面上的电荷存储结构以及覆盖第一和第二侧表面上的电荷存储结构的栅极结构。 通道体具有小于阈值通道体深度的第一和第二侧表面之间的深度，与构成该单元的有效通道长度大于阈值长度的栅极结构组合。 通道体深度与有效沟道长度的组合是相关联的，使得单元通道体可以完全耗尽，并且当存储单元在读取偏压下具有高阈值状态时，可以抑制亚阈值泄漏电流。