公开(公告)号：US07092300B2

公开(公告)日：2006-08-15

申请号：US10822997

申请日：2004-04-13

申请人： Jean-Marc Dortu ,  Wolfgang Spirkl

发明人： Jean-Marc Dortu ,  Wolfgang Spirkl

IPC分类号： G11C7/10

CPC分类号： G11C11/4076 ,  G11C7/22 ,  G11C2207/2281 ,  G11C2207/229

摘要： Memory apparatus having a short word line cycle time and method for operating a memory apparatus. One embodiment provides a memory apparatus comprising at least one cell array having a multiplicity of memory cells, with each of the memory cells having an associated word line and an associated bit line; a control device which has a signaling connection to the word lines and to the bit lines and is configured to read data stored in the memory cells and to write data to the memory cells; wherein the control device is configured to execute a destructive read command (DRD) for reading data from at least one of the memory cells, comprising: electrically biasing a bit line associated with the at least one memory cell, opening a word line associated with the at least one memory cell, and destructively reading data stored in the at least one memory cell.

摘要翻译： 具有短字线周期时间的存储装置和用于操作存储装置的方法。 一个实施例提供了一种存储器装置，其包括具有多个存储器单元的至少一个单元阵列，其中每个存储器单元具有相关联的字线和相关联的位线; 控制装置，其具有与字线和位线的信令连接，并且被配置为读取存储在存储器单元中的数据并将数据写入存储器单元; 其中所述控制设备被配置为执行用于从所述存储器单元中的至少一个读取数据的破坏性读取命令（DRD），包括：电气偏置与所述至少一个存储器单元相关联的位线，打开与所述至少一个存储器单元相关联的字线 至少一个存储器单元，并且破坏性地读取存储在所述至少一个存储器单元中的数据。

公开(公告)号：US20050108603A1

公开(公告)日：2005-05-19

申请号：US10988541

申请日：2004-11-16

申请人： Wolfgang Spirkl ,  Ralf Arnold

发明人： Wolfgang Spirkl ,  Ralf Arnold

IPC分类号： G01R31/28 ,  G01R31/317 ,  G01R31/3177 ,  G01R31/3185 ,  G06F11/00 ,  G11C29/02 ,  H01L21/66

CPC分类号： G11C29/022 ,  G01R31/31716 ,  G01R31/318533 ,  G11C29/02

摘要： Unidirectional input switching arrangements or pad circuits are supplemented by transfer switching devices employed to route an internal test signal to the input of an input driver in the unidirectional input switching arrangement and to couple it to an internal switching logic unit. The transfer switching devices are controlled via a multiplexer unit, which for its part can be programmed directly using boundary scan registers. The present invention allows all unidirectional pad circuits or input drivers to be tested in the course of a reduced I/O test method for semiconductor circuits, in which testing internal circuits in the semiconductor circuit involves only a subset of the signal connections associated with the input drivers being coupled to a test apparatus.

摘要翻译： 单向输入切换装置或焊盘电路由用于将内部测试信号路由到单向输入切换装置中的输入驱动器的输入并将其耦合到内部开关逻辑单元的传输开关装置进行补充。 传输切换设备通过多路复用器单元进行控制，该单元可以使用边界扫描寄存器直接进行编程。 本发明允许在用于半导体电路的减少的I / O测试方法的过程中测试所有单向焊盘电路或输入驱动器，其中半导体电路中的测试内部电路仅涉及与输入相关联的信号连接的子集 驱动器耦合到测试装置。

公开(公告)号：US06812689B2

公开(公告)日：2004-11-02

申请号：US09898816

申请日：2001-07-03

申请人： Gunnar Krause ,  Wolfgang Spirkl

发明人： Gunnar Krause ,  Wolfgang Spirkl

IPC分类号： G01R3100

CPC分类号： G01R19/003

摘要： A method and device for measuring voltage of an internal reference voltage source of an integrated semiconductor circuit, in particular, a DRAM, including the steps of comparing a reference voltage to an external comparison voltage with a comparator, forming a measured value for the reference voltage to be set in accordance with a comparison result, switching a commutator by a clock- or software-control to alternatively apply the reference voltage and the comparison voltage to the comparator inputs at the same time, varying one of the reference and comparison voltage to a setpoint voltage value until the comparator output changes its logic value at each commutator switched stage, buffering the voltage values present for each switched state when the logic value changes, forming an average value for the reference voltage from the stored voltage values, and setting the reference voltage as a function of the average value formed.

摘要翻译： 一种用于测量集成半导体电路，特别是DRAM的内部参考电压源的电压的方法和装置，包括将参考电压与外部比较电压与比较器进行比较的步骤，形成参考电压的测量值 根据比较结果设置，通过时钟或软件控制切换换向器以交替地将参考电压和比较电压同时施加到比较器输入，将参考电压和比较电压之一改变为 直到比较器输出在每个换向器切换级改变其逻辑值，缓冲当逻辑值改变时针对每个切换状态存在的电压值，从存储的电压值形成参考电压的平均值，并设置参考值 电压作为形成的平均值的函数。

公开(公告)号：US20090222779A1

公开(公告)日：2009-09-03

申请号：US12039292

申请日：2008-02-28

申请人： Thomas Nirmaier ,  Wolfgang Spirkl

发明人： Thomas Nirmaier ,  Wolfgang Spirkl

IPC分类号： G06F17/50 ,  G06F11/00

CPC分类号： G11C29/56 ,  G01R31/318357 ,  G01R31/318385 ,  G11C29/56004

摘要： Methods and apparatuses for generating a random sequence of commands for a semiconductor device. The method generates random state transitions within a finite state machine model of the semiconductor device. A sequence of commands is determined which are associated to the generated random state transitions based on the finite state machine model of the semiconductor device.

摘要翻译： 用于产生用于半导体器件的随机指令序列的方法和装置。 该方法在半导体器件的有限状态机模型内产生随机状态转换。 基于半导体器件的有限状态机模型，确定与生成的随机状态转换相关联的命令序列。

公开(公告)号：US20080232233A1

公开(公告)日：2008-09-25

申请号：US12050522

申请日：2008-03-18

申请人： Wolfgang Spirkl ,  Holger Steffens

发明人： Wolfgang Spirkl ,  Holger Steffens

IPC分类号： H04J15/00

CPC分类号： G11C7/02 ,  G11C11/4076 ,  G11C11/4096 ,  G11C11/4097

摘要： A device for reducing mutual crosstalk of a signal routed across a first line and a second signal routed across a second line, wherein by the mutual crosstalk at an output of the first line a first interfered signal may be obtained and at an output of the second line a second interfered signal may be obtained, comprising a modifier for modifying the first interfered signal that is interfered by crosstalk due to the second signal, and for modifying the second interfered signal that is interfered by crosstalk due to the first signal, wherein the modifier is adapted to model an interference due to the mutual crosstalk, and a combiner for combining the first interfered signal with the modified second interfered signal to obtain a first corrected signal and for combining the second interfered signal with the modified first interfered signal to obtain a second corrected signal.

摘要翻译： 一种用于减少跨越第一线路路由的信号的相互串扰的设备和跨越第二线路路由的第二信号，其中通过第一线路的输出处的相互串扰可以获得第一干扰信号，并且在第二线路的输出端 可以获得第二干扰信号，包括用于修改由于第二信号而被串扰干扰的第一干扰信号的修改器，以及用于修改由于第一信号而被串扰干扰的第二干扰信号，其中修饰符 适于对由于相互串扰造成的干扰进行建模，以及用于将第一干扰信号与修改的第二干扰信号组合以获得第一校正信号并将第二干扰信号与修改的第一干扰信号组合以获得第二干扰信号的组合器 校正信号。

公开(公告)号：US07308628B2

公开(公告)日：2007-12-11

申请号：US10988541

申请日：2004-11-16

申请人： Wolfgang Spirkl ,  Ralf Arnold

发明人： Wolfgang Spirkl ,  Ralf Arnold

IPC分类号： G01R31/28

CPC分类号： G11C29/022 ,  G01R31/31716 ,  G01R31/318533 ,  G11C29/02

摘要： Transfer switching devices, which supplement unidirectional input switching arrangements or pad circuits are employed to route an internal test signal to the input of an input driver in the unidirectional input switching arrangement and to couple the internal test signal to an internal switching logic unit. The transfer switching devices are controlled via a multiplexer unit, which can be programmed directly using boundary scan registers. The present invention allows all unidirectional pad circuits or input drivers to be tested in the course of a reduced I/O test method for semiconductor circuits, in which testing internal circuits in the semiconductor circuit involves only a subset of the signal connections associated with the input drivers being coupled to a test apparatus.

摘要翻译： 采用补充单向输入切换装置或焊盘电路的转换开关装置将内部测试信号路由到单向输入开关装置中的输入驱动器的输入端，并将内部测试信号耦合到内部开关逻辑单元。 转换开关器件通过多路复用器单元进行控制，该单元可以使用边界扫描寄存器直接编程。 本发明允许在用于半导体电路的减少的I / O测试方法的过程中测试所有单向焊盘电路或输入驱动器，其中半导体电路中的测试内部电路仅涉及与输入相关联的信号连接的子集 驱动器耦合到测试装置。

公开(公告)号：US07299447B2

公开(公告)日：2007-11-20

申请号：US10238819

申请日：2002-09-10

申请人： Wolfgang Spirkl

发明人： Wolfgang Spirkl

IPC分类号： G06F9/44 ,  G06F17/50 ,  G06F9/45 ,  G06F19/00

CPC分类号： G06F11/261

摘要： An electrical circuit can be described with a reference model that has a plurality of states and a plurality of state transitions. Acceptable and/or unacceptable instruction sets are predefined for each state. Acceptable and unacceptable instruction sets are generated randomly in succession from the reference model and applied to a mapping of the electrical circuit for processing. By comparing the instruction sets processed by the mapping of the electrical circuit with the instruction sets determined from the reference model, conclusive information relating to the mapping of the electrical circuit is obtained.

摘要翻译： 可以用具有多个状态和多个状态转换的参考模型描述电路。 为每个状态预定义可接受的和/或不可接受的指令集。 从参考模型中连续生成可接受和不可接受的指令集，并将其应用于用于处理的电路的映射。 通过将由电路映射处理的指令集与从参考模型确定的指令集进行比较，获得与电路映射有关的确定信息。

公开(公告)号：US06910163B2

公开(公告)日：2005-06-21

申请号：US10210015

申请日：2002-07-31

申请人： Thomas Janik ,  Sebastian Kuhne ,  Roderick McConnell ,  Detlev Richter ,  Wolfgang Spirkl

发明人： Thomas Janik ,  Sebastian Kuhne ,  Roderick McConnell ,  Detlev Richter ,  Wolfgang Spirkl

IPC分类号： G11C29/44 ,  G11C29/48 ,  G11C29/00

CPC分类号： G11C29/44 ,  G11C29/48

摘要： A method and a configuration for the output of bit error tables from semiconductor devices are described. A test control unit reads the bit error table from the memory device following a request from the test apparatus. Then, the bit error tables are transmitted sequentially to the test apparatus for further processing.

摘要翻译： 描述了用于从半导体器件输出位错误表的方法和配置。 测试控制单元根据来自测试设备的请求从存储设备读取位错误表。 然后，将比特错误表依次发送到测试装置进一步处理。

公开(公告)号：US06639862B2

公开(公告)日：2003-10-28

申请号：US10105547

申请日：2002-03-25

申请人： Wolfgang Spirkl

发明人： Wolfgang Spirkl

IPC分类号： G11C700

CPC分类号： G11C11/4091 ,  G11C11/406 ,  G11C11/4094

摘要： To carry out a refresh operation, a semiconductor memory having dynamic memory cells includes a sense amplifier that, on the output side, provides a signal depending on a control of a bit line driver. The bit line driver is embodied as an adiabatic amplifier, preferably, having current paths through which charges that are to be exchanged during a charge-reversal operation are buffer-stored in capacitors. Power loss for the charge reversal of the bit line capacitances is thereby saved. A method for operating the memory is also provided.

公开(公告)号：US08635393B2

公开(公告)日：2014-01-21

申请号：US11333758

申请日：2006-01-17

申请人： Jean-Marc Dortu ,  Wolfgang Spirkl

发明人： Jean-Marc Dortu ,  Wolfgang Spirkl

IPC分类号： G06F12/06

CPC分类号： G11C7/1051 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4096

摘要： The invention relates to a method for reading data from a semiconductor memory, said method comprising the following steps in this order: providing at least one first memory bank and at least one shadow memory bank which are each designed to store a multiplicity of binary data items, the same data as in the first memory bank being stored in the shadow memory bank; receiving a command for reading data which are to be read from the first memory bank; utilizing a state checking device of the semiconductor memory to check whether the first memory bank is in an open memory bank state, and, if the first memory bank is in the open memory bank state, reading the data which are to be read from the at least one shadow memory bank, and, if the first memory bank is not in the open memory bank state, reading the data which are to be read from the first memory bank, the open memory state being such a memory state of the memory bank which does not allow the data which are to be read to be read without previously closing an open word line of the memory bank. The invention also relates to a corresponding semiconductor memory.

摘要翻译： 本发明涉及一种用于从半导体存储器读取数据的方法，所述方法包括以下步骤：提供至少一个第一存储体和至少一个影子存储体，每个阴影存储体被设计成存储多个二进制数据项 与第一存储体中相同的数据存储在阴影存储体中; 接收用于读取要从第一存储体读取的数据的命令; 利用半导体存储器的状态检查装置来检查第一存储体是否处于开放存储器组状态，并且如果第一存储体处于开放存储体状态，则读取要从其读取的数据 至少一个影子存储器组，并且如果第一存储体不处于开放存储体状态，则读取要从第一存储体读取的数据，则开放存储器状态是存储体的存储状态， 不允许在未先前关闭存储体的打开字线的情况下读取要读取的数据。 本发明还涉及相应的半导体存储器。