公开(公告)号：US07092300B2

公开(公告)日：2006-08-15

申请号：US10822997

申请日：2004-04-13

申请人： Jean-Marc Dortu ,  Wolfgang Spirkl

发明人： Jean-Marc Dortu ,  Wolfgang Spirkl

IPC分类号： G11C7/10

CPC分类号： G11C11/4076 ,  G11C7/22 ,  G11C2207/2281 ,  G11C2207/229

摘要： Memory apparatus having a short word line cycle time and method for operating a memory apparatus. One embodiment provides a memory apparatus comprising at least one cell array having a multiplicity of memory cells, with each of the memory cells having an associated word line and an associated bit line; a control device which has a signaling connection to the word lines and to the bit lines and is configured to read data stored in the memory cells and to write data to the memory cells; wherein the control device is configured to execute a destructive read command (DRD) for reading data from at least one of the memory cells, comprising: electrically biasing a bit line associated with the at least one memory cell, opening a word line associated with the at least one memory cell, and destructively reading data stored in the at least one memory cell.

摘要翻译： 具有短字线周期时间的存储装置和用于操作存储装置的方法。 一个实施例提供了一种存储器装置，其包括具有多个存储器单元的至少一个单元阵列，其中每个存储器单元具有相关联的字线和相关联的位线; 控制装置，其具有与字线和位线的信令连接，并且被配置为读取存储在存储器单元中的数据并将数据写入存储器单元; 其中所述控制设备被配置为执行用于从所述存储器单元中的至少一个读取数据的破坏性读取命令（DRD），包括：电气偏置与所述至少一个存储器单元相关联的位线，打开与所述至少一个存储器单元相关联的字线 至少一个存储器单元，并且破坏性地读取存储在所述至少一个存储器单元中的数据。

公开(公告)号：US08635393B2

公开(公告)日：2014-01-21

申请号：US11333758

申请日：2006-01-17

申请人： Jean-Marc Dortu ,  Wolfgang Spirkl

发明人： Jean-Marc Dortu ,  Wolfgang Spirkl

IPC分类号： G06F12/06

CPC分类号： G11C7/1051 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4096

摘要： The invention relates to a method for reading data from a semiconductor memory, said method comprising the following steps in this order: providing at least one first memory bank and at least one shadow memory bank which are each designed to store a multiplicity of binary data items, the same data as in the first memory bank being stored in the shadow memory bank; receiving a command for reading data which are to be read from the first memory bank; utilizing a state checking device of the semiconductor memory to check whether the first memory bank is in an open memory bank state, and, if the first memory bank is in the open memory bank state, reading the data which are to be read from the at least one shadow memory bank, and, if the first memory bank is not in the open memory bank state, reading the data which are to be read from the first memory bank, the open memory state being such a memory state of the memory bank which does not allow the data which are to be read to be read without previously closing an open word line of the memory bank. The invention also relates to a corresponding semiconductor memory.

摘要翻译： 本发明涉及一种用于从半导体存储器读取数据的方法，所述方法包括以下步骤：提供至少一个第一存储体和至少一个影子存储体，每个阴影存储体被设计成存储多个二进制数据项 与第一存储体中相同的数据存储在阴影存储体中; 接收用于读取要从第一存储体读取的数据的命令; 利用半导体存储器的状态检查装置来检查第一存储体是否处于开放存储器组状态，并且如果第一存储体处于开放存储体状态，则读取要从其读取的数据 至少一个影子存储器组，并且如果第一存储体不处于开放存储体状态，则读取要从第一存储体读取的数据，则开放存储器状态是存储体的存储状态， 不允许在未先前关闭存储体的打开字线的情况下读取要读取的数据。 本发明还涉及相应的半导体存储器。

公开(公告)号：US20050135139A1

公开(公告)日：2005-06-23

申请号：US10822997

申请日：2004-04-13

申请人： Jean-Marc Dortu ,  Wolfgang Spirkl

发明人： Jean-Marc Dortu ,  Wolfgang Spirkl

IPC分类号： G11C7/22 ,  G11C11/4076 ,  G11C11/22

CPC分类号： G11C11/4076 ,  G11C7/22 ,  G11C2207/2281 ,  G11C2207/229

摘要： Memory apparatus having a short word line cycle time and method for operating a memory apparatus. One embodiment provides a memory apparatus comprising at least one cell array having a multiplicity of memory cells, with each of the memory cells having an associated word line and an associated bit line; a control device which has a signaling connection to the word lines and to the bit lines and is configured to read data stored in the memory cells and to write data to the memory cells; wherein the control device is configured to execute a destructive read command (DRD) for reading data from at least one of the memory cells, comprising: electrically biasing a bit line associated with the at least one memory cell, opening a word line associated with the at least one memory cell, and destructively reading data stored in the at least one memory cell.

摘要翻译： 具有短字线周期时间的存储装置和用于操作存储装置的方法。 一个实施例提供了一种存储器装置，其包括具有多个存储器单元的至少一个单元阵列，其中每个存储器单元具有相关联的字线和相关联的位线; 控制装置，其具有与字线和位线的信令连接，并且被配置为读取存储在存储器单元中的数据并将数据写入存储器单元; 其中所述控制设备被配置为执行用于从所述存储器单元中的至少一个读取数据的破坏性读取命令（DRD），包括：电气偏置与所述至少一个存储器单元相关联的位线，打开与所述至少一个存储器单元相关联的字线 至少一个存储器单元，并且破坏性地读取存储在所述至少一个存储器单元中的数据。

公开(公告)号：US20070030751A1

公开(公告)日：2007-02-08

申请号：US11333758

申请日：2006-01-17

申请人： Jean-Marc Dortu ,  Wolfgang Spirkl

发明人： Jean-Marc Dortu ,  Wolfgang Spirkl

IPC分类号： G11C8/00

CPC分类号： G11C7/1051 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4096

摘要： The invention relates to a method for reading data from a semiconductor memory, said method comprising the following steps in this order: providing at least one first memory bank and at least one shadow memory bank which are each designed to store a multiplicity of binary data items, the same data as in the first memory bank being stored in the shadow memory bank; receiving a command for reading data which are to be read from the first memory bank; utilizing a state checking device of the semiconductor memory to check whether the first memory bank is in an open memory bank state, and, if the first memory bank is in the open memory bank state, reading the data which are to be read from the at least one shadow memory bank, and, if the first memory bank is not in the open memory bank state, reading the data which are to be read from the first memory bank, the open memory state being such a memory state of the memory bank which does not allow the data which are to be read to be read without previously closing an open word line of the memory bank. The invention also relates to a corresponding semiconductor memory.

摘要翻译： 本发明涉及一种用于从半导体存储器读取数据的方法，所述方法包括以下步骤：提供至少一个第一存储体和至少一个影子存储体，每个阴影存储体被设计成存储多个二进制数据项 与第一存储体中相同的数据存储在阴影存储体中; 接收用于读取要从第一存储体读取的数据的命令; 利用半导体存储器的状态检查装置来检查第一存储体是否处于开放存储器组状态，并且如果第一存储体处于开放存储体状态，则读取要从其读取的数据 至少一个影子存储器组，并且如果第一存储体不处于开放存储体状态，则读取要从第一存储体读取的数据，则开放存储器状态是存储体的存储状态， 不允许在未先前关闭存储体的打开字线的情况下读取要读取的数据。 本发明还涉及相应的半导体存储器。

公开(公告)号：US06781220B2

公开(公告)日：2004-08-24

申请号：US10160446

申请日：2002-05-30

申请人： Andreas Täube ,  Jean-Marc Dortu ,  Paul Schmölz ,  Robert Feurle

发明人： Andreas Täube ,  Jean-Marc Dortu ,  Paul Schmölz ,  Robert Feurle

IPC分类号： H01L23495

CPC分类号： H01L23/49838 ,  H01L23/50 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/45144 ,  H01L2224/4824 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00015

摘要： In a semiconductor memory device, a printed circuit board connects a memory chip to an external circuit. The printed circuit board includes a multiplicity of pads arranged in a column. These pads connect the board to the memory chip. The board also includes a multiplicity of data terminals arranged in at least two columns and connected to the pads by data connections. The data connections are configured such that each data connection has essentially the same electrical properties as any other data connection.

摘要翻译： 在半导体存储器件中，印刷电路板将存储芯片连接到外部电路。 印刷电路板包括布置在列中的多个焊盘。 这些焊盘将电路板连接到存储器芯片。 该板还包括布置在至少两列中并通过数据连接连接到焊盘的多个数据终端。 配置数据连接使得每个数据连接具有与任何其他数据连接基本相同的电气特性。

公开(公告)号：US06707705B2

公开(公告)日：2004-03-16

申请号：US10113413

申请日：2002-04-01

申请人： Paul Schmölz ,  Jean-Marc Dortu ,  Robert Feurle ,  Andreas Täuber

发明人： Paul Schmölz ,  Jean-Marc Dortu ,  Robert Feurle ,  Andreas Täuber

IPC分类号： G11C1124

CPC分类号： G11C7/222 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4085

摘要： In order to operate an integrated dynamic memory having a memory cell array having bit lines and word lines a plurality of individual actions—to be performed for a memory access—from the activation of one of the word lines up to the precharging of the word lines are controlled in a synchronized manner with a clock signal. A value for defining a defined number of clock cycles between at least two individual actions is programmed at the beginning. For this purpose, a control circuit has a programmable unit. In this way, in conjunction with a clocked circuit, a comparatively high data throughput is made possible even at variable clock frequencies.

摘要翻译： 为了操作具有存储单元阵列的集成动态存储器，该存储单元阵列具有位线和字线，用于执行存储器访问的多个单独动作 - 从一行字线的激活直到字线预充电 以时钟信号的同步方式进行控制。 在开始时，编写一个用于定义至少两个单独动作之间定义数量的时钟周期的值。 为此，控制电路具有可编程单元。 以这种方式，结合时钟电路，即使在可变时钟频率下也可以实现相对较高的数据吞吐量。

公开(公告)号：US07467254B2

公开(公告)日：2008-12-16

申请号：US11041084

申请日：2005-01-21

申请人： Jean-Marc Dortu

发明人： Jean-Marc Dortu

IPC分类号： G06F13/00 ,  G06F12/00

CPC分类号： G06F12/1433

摘要： The invention provides a semiconductor memory device that includes at least two memory banks. The semiconductor memory device is designed in such a way that: at least two processor units can carry out read accesses and write accesses to memory banks; and by means of an inhibit command communicated by one of the processor units, the write access by the processor unit which has communicated the inhibit command and/or by at least one of the other processor units to the inhibited memory bank is prevented at least occasionally. A circuit arrangement including the above semiconductor memory device is furthermore proposed.

摘要翻译： 本发明提供一种包括至少两个存储体的半导体存储器件。 半导体存储器件被设计成：至少两个处理器单元可以执行对存储体的读访问和写存取; 并且通过由处理器单元之一传送的禁止命令，至少偶尔地防止已经传送禁止命令的处理器单元和/或其他处理器单元中的至少一个到禁止存储器组的写访问 。 此外还提出了包括上述半导体存储器件的电路装置。

公开(公告)号：US20050195670A1

公开(公告)日：2005-09-08

申请号：US11063495

申请日：2005-02-22

申请人： Jean-Marc Dortu

发明人： Jean-Marc Dortu

IPC分类号： G11C5/14 ,  G11C7/00 ,  G11C7/08 ,  G11C11/4063

CPC分类号： G11C7/08 ,  G11C11/40615 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4097

摘要： Semiconductor memory apparatus and methods of operating the same are provided. The apparatus has at least one first sense amplifier for amplifying a voltage level which has been read from a memory cell when the semiconductor memory apparatus is in an active operating mode and at least one second sense amplifier for amplifying a voltage level which has been read from the memory cell when the semiconductor memory apparatus is in a refresh operating mode. The apparatus is designed such that either the first or the second sense amplifier can be placed in electrical contact with the memory cell and the capacitance of the second sense amplifier is lower than the capacitance of the first sense amplifier.

摘要翻译： 提供半导体存储装置及其操作方法。 该装置具有至少一个第一读出放大器，用于在半导体存储器件处于主动工作模式时放大从存储器单元读取的电压电平;以及至少一个第二读出放大器，用于放大已经读取的电压电平 当半导体存储装置处于刷新操作模式时的存储单元。 该装置被设计成使得第一或第二读出放大器可以被放置成与存储单元电接触，并且第二读出放大器的电容低于第一读出放大器的电容。

公开(公告)号：US06922764B2

公开(公告)日：2005-07-26

申请号：US10299750

申请日：2002-11-19

申请人： Jean-Marc Dortu ,  Robert Feurle ,  Paul Schmölz ,  Andreas Täuber

发明人： Jean-Marc Dortu ,  Robert Feurle ,  Paul Schmölz ,  Andreas Täuber

IPC分类号： G11C7/10 ,  G06F12/00

CPC分类号： G11C7/1006 ,  G11C2207/229

摘要： A memory is provided which has a memory region for storing data, an input for receiving a data bundle with a plurality of temporally sequential data blocks and an input for receiving a data mask signal which is assigned to the data bundle. The memory also has a unit for receiving a data block from the plurality of temporally sequential data bundle data blocks which is to be written into the memory region in dependence on the data mask signal. The memory also includes a unit for writing the received data block into the memory region.

摘要翻译： 提供了一种存储器，其具有用于存储数据的存储区域，用于接收具有多个时间顺序数据块的数据束的输入端和用于接收分配给数据束的数据掩码信号的输入端。 存储器还具有一个单元，用于根据数据掩码信号从要被写入存储器区域的多个时间上顺序的数据束数据块接收数据块。 存储器还包括用于将接收的数据块写入存储器区域的单元。

公开(公告)号：US06646908B2

公开(公告)日：2003-11-11

申请号：US10113415

申请日：2002-04-01

申请人： Andreas Täuber ,  Robert Feurle ,  Paul Schmölz ,  Jean-Marc Dortu

发明人： Andreas Täuber ,  Robert Feurle ,  Paul Schmölz ,  Jean-Marc Dortu

IPC分类号： G11C1124

CPC分类号： G11C7/1006 ,  G11C11/4093

摘要： The integrated memory chip has an external control terminal, a dynamic memory, and a control circuit for controlling a memory access to the dynamic memory. The control circuit is connected to the external control terminal, for receiving an access command indicating the beginning of a memory access. The control circuit further has an output, which is connected to the dynamic memory, for outputting at least one activation signal, read command or write command and precharge command generated from the access command. This makes it possible, in the case of use in a data processing system, to dispense with a DRAM controller provided outside the memory chip.