公开(公告)号：US20070058470A1

公开(公告)日：2007-03-15

申请号：US11227585

申请日：2005-09-15

申请人： Klaus Nierle ,  Martin Versen

发明人： Klaus Nierle ,  Martin Versen

IPC分类号： G11C7/00

CPC分类号： G11C5/04 ,  H05K1/181 ,  H05K2201/10159 ,  H05K2201/10212 ,  Y02P70/611

摘要： Methods and apparatus for accessing serial presence detect data are provided. For some embodiments, serial presence detect logic is incorporated in memory devices, eliminating the need for a separate serial presence detect component.

摘要翻译： 提供了访问串行存在检测数据的方法和装置。 对于一些实施例，将串行存在检测逻辑并入存储器件中，从而消除对单独的串行存在检测组件的需要。

公开(公告)号：US07120070B2

公开(公告)日：2006-10-10

申请号：US10930132

申请日：2004-08-31

申请人： Martin Versen ,  Klaus Nierle

发明人： Martin Versen ,  Klaus Nierle

IPC分类号： G11C7/00

CPC分类号： G11C29/026 ,  G11C11/401 ,  G11C29/02 ,  G11C29/025

摘要： DRAM memory device (1) comprising at least one array of memory cells (2, 3, 4, 5), each memory cell (12) being connected to a bit line (BL) and a word line (WL), each of said bit lines (BL) being connected to a sense amplifier and a pre-charge circuit (15); a controllable active-current generator (7, 8, 9, 10) for providing power to the sense amplifiers and pre-charge circuits (15) for a time interval that is limited by a time at which a command for a read or write access is applied to the DRAM memory device (1) and an assigned switching time; a controllable standby-current generator (6) for providing power to the sense amplifiers and pre-charge circuits (15) after the switching time; a control circuit (11) for receiving external data, address and control signals (C, A, D) and for controlling the active-current generator (7, 8, 9, 10) and the standby-current generator (6); wherein the control circuit (11) is adapted to control the time for switching the respective power generator (6, 7, 8, 9, 10) to the sense amplifiers and to the pre-charge circuits (15) subject to an external test mode signal for reducing the overall testing time in a test of the serviceability of the bit lines (BL), sense amplifiers and pre-charge circuits (15).

摘要翻译： DRAM存储器件（1）包括至少一个存储器单元阵列（2,3,4,5），每个存储器单元（12）连接到位线（BL）和字线（WL），每个所述存储器单元 位线（BL）连接到读出放大器和预充电电路（15）; 一个可控有功电流发生器（7,8,9,10），用于在读或写访问命令的时间限制的时间间隔内向读出放大器和预充电电路（15）提供功率 被施加到DRAM存储器件（1）和分配的切换时间; 用于在切换时间之后向读出放大器和预充电电路（15）提供电力的可控待机电流发生器（6）; 用于接收外部数据，地址和控制信号（C，A，D）并用于控制有功电流发生器（7,8,9,10）和待机电流发生器（6）的控制电路（11）。 其中所述控制电路（11）适于控制用于将各个发电机（6,7,8,9,10）切换到所述读出放大器和经受外部测试模式的所述预充电电路（15）的时间 用于在测试位线（BL），读出放大器和预充电电路（15）的可用性的测试中减少总体测试时间的信号。

公开(公告)号：US20060053354A1

公开(公告)日：2006-03-09

申请号：US11214482

申请日：2005-08-29

申请人： Jorg Kliewer ,  Martin Versen

发明人： Jorg Kliewer ,  Martin Versen

IPC分类号： G11C29/00

CPC分类号： G11C29/02 ,  G11C5/04 ,  G11C29/025

摘要： The invention relates to a test method for determining a wire configuration for a circuit carrier having at least one component arranged thereon, where internal lines in the component are connected to component connections in a prescribed order, and where the component connections are wired to connections on the circuit carrier. According to the method, a respective prescribed test signal is applied to each internal line of the component using a controllable test signal generator integrated in the component. Output signals applied to the connections of the circuit carrier are tapped off. Thereafter, the respective output signals tapped off are identified with the corresponding test signals applied to the internal lines of the component using an external test apparatus for determining the wire configuration between the component connections and circuit carrier connections.

摘要翻译： 本发明涉及一种用于确定具有布置在其上的至少一个部件的电路载体的导线配置的测试方法，其中部件中的内部线以规定的顺序连接到部件连接，并且其中部件连接被连接到 电路载体。 根据该方法，使用集成在该部件中的可控测试信号发生器将各个规定的测试信号施加到部件的每条内部线路。 施加到电路载体的连接的输出信号被分接。 此后，使用用于确定部件连接和电路载体连接之间的导线配置的外部测试装置，利用施加到部件的内部线路的相应测试信号来识别各个输出信号。

公开(公告)号：US20050209715A1

公开(公告)日：2005-09-22

申请号：US11081270

申请日：2005-03-16

申请人： Manfred Moser ,  Erwin Thalmann ,  Martin Versen

发明人： Manfred Moser ,  Erwin Thalmann ,  Martin Versen

IPC分类号： G01R31/3177 ,  G06F11/00 ,  G11C29/48 ,  H02H3/24

CPC分类号： G11C29/48 ,  G11C2029/5602

摘要： Monitoring device for monitoring internal signals during initialization of an electronic circuit unit The invention provides a device for monitoring electronic circuit units during an initialization phase. The device has at least one internal data line (103) for forwarding internal data (105) in the electronic circuit unit (101) and at least one data connection line (104) for outputting the internal data from the electronic circuit unit (101) and for inputting external data (106) into the electronic circuit unit (101). A changeover unit (102), which is intended to change over the data connection line (104) either to the internal data line (103) or to internal signal lines (113), and a combinational logic unit (111) for combining an initialization signal (109), which is provided by the electronic circuit unit (101) to be monitored, with an external changeover signal (108), which is supplied via a changeover signal input (107) of the electronic circuit unit (101) to be monitored, are also provided. An activation signal (114), which is output by the changeover unit (102), is used to change over the data connection line to the internal signal lines (113) when the initialization signal (109) indicates an initialization mode of the electronic circuit unit (101).

摘要翻译： 用于在电子电路单元的初始化期间监视内部信号的监视装置本发明提供了一种用于在初始化阶段期间监视电子电路单元的装置。 该装置具有至少一个内部数据线（103），用于转发电子电路单元（101）中的内部数据（105）和用于从电子电路单元（101）输出内部数据的至少一个数据连接线（104） 并将外部数据（106）输入到电子电路单元（101）中。 用于将数据连接线（104）切换到内部数据线（103）或内部信号线（113）的转换单元（102）以及用于组合初始化的组合逻辑单元（111） 由待监视的电子电路单元（101）提供的信号（109）与通过电子电路单元（101）的转换信号输入（107）提供的外部转换信号（108）成为 也被提供。 当初始化信号（109）指示电子电路的初始化模式时，由切换单元（102）输出的激活信号（114）用于将数据连接线切换到内部信号线（113） 单位（101）。

公开(公告)号：US20050114734A1

公开(公告)日：2005-05-26

申请号：US10933645

申请日：2004-09-03

申请人： Peter Beer ,  Achim Schramm ,  Martin Versen

发明人： Peter Beer ,  Achim Schramm ,  Martin Versen

IPC分类号： G11C29/50 ,  G06F11/00

CPC分类号： G11C29/50012 ,  G11C11/401 ,  G11C29/50

摘要： Apparatus and method for checking output signals of an integrated circuit are provided. One embodiment provides a method for checking whether signals are output by a write circuit of an integrated circuit according to a predefined specification. In this context, the high precision of an external test device which is inherent to the system is used to check, within a module, that a data signal and a data sampling signal of the integrated circuit are output according to a specification.

摘要翻译： 提供了用于检查集成电路的输出信号的装置和方法。 一个实施例提供了一种用于根据预定义的规范来检查信号是否由集成电路的写入电路输出的方法。 在这种情况下，系统固有的外部测试装置的高精度用于在模块内检查根据规格输出集成电路的数据信号和数据采样信号。

公开(公告)号：US06862234B2

公开(公告)日：2005-03-01

申请号：US10798245

申请日：2004-03-11

申请人： Martin Versen ,  Peter Beer ,  Lee Nino

发明人： Martin Versen ,  Peter Beer ,  Lee Nino

IPC分类号： G11C29/02 ,  G11C29/00

CPC分类号： G11C29/026 ,  G11C11/401 ,  G11C29/02

摘要： Method and system for testing a sense amplifier in a dynamic memory circuit. In one embodiment, the sense amplifier is connected to a first bit line pair via a first switching device and to a second bit line pair via a second switching device. First memory cells are arranged at crossover points between first word lines and one of the bit lines of the first bit line pair, and second memory cells are arranged at crossover points between second word lines and one of the bit lines of the second bit line pair. Data are written to the first and the second memory cells and subsequently read out. During the read-out of one of the first memory cells, the relevant first word line is activated and the first switching device is activated while the second switching device is closed, and during the read-out of one of the second memory cells, the relevant second word line is activated and the second switching device is activated while the first switching device being closed. One of the first and one of the second memory cells are read in a sequence such that the first and the second switching device are switched multiply during the test of the first and second memory cells.

摘要翻译： 用于测试动态存储器电路中的读出放大器的方法和系统。 在一个实施例中，读出放大器经由第一开关装置连接到第一位线对，经由第二开关装置连接到第二位线对。 第一存储单元布置在第一字线和第一位线对之一的位线之间的交叉点处，并且第二存储器单元布置在第二字线与第二位线对之一的位线之间的交叉点处 。 数据被写入第一和第二存储单元，随后读出。 在读出第一存储器单元之一期间，相关的第一字线被激活，并且第一开关器件在第二开关器件闭合时被激活，并且在读出第二存储单元之一期间， 相关的第二字线被激活，并且第二开关器件在第一开关器件闭合时被激活。 以第一和第二存储器单元中的第一个存储单元中的一个按顺序读取，使得第一和第二开关器件在第一和第二存储器单元的测试期间被倍增。