公开(公告)号：US20080265944A1

公开(公告)日：2008-10-30

申请号：US11686560

申请日：2007-03-15

申请人： SATOSHI MURAOKA ,  Norio Chujo ,  Ritsuro Orihashi

发明人： SATOSHI MURAOKA ,  Norio Chujo ,  Ritsuro Orihashi

IPC分类号： H03K19/0185 ,  H03K19/0175

CPC分类号： H03K19/018521

摘要： In an output buffer circuit including Inverter 1 to Inverter 3, Delay Circuit 1 to Delay Circuit 3 for delaying an input signal for a specific time, Buffer 1 to Buffer 3, and a function for transmitting a logic signal to a transmission path and in accordance with an amount of signal attenuation in the transmission path, creating at a transmission side a waveform including four or more kinds of signal voltages, the preemphasis amount is made variable and the ON resistance Rs of the buffer is made constant. Selector circuit 1 to Selector circuit 3 are situated before the buffers, the inverter, capable of selecting through selector logic a signal to be inputted to the buffer, inverts a data signal, and the preemphasis amount and the number of preemphasis taps are adjusted through a selection signal for the selector logic.

摘要翻译： 在包括变频器1至变频器3的输出缓冲电路中，延迟电路1至延迟电路3用于将输入信号延迟特定时间，缓冲器1至缓冲器3，以及用于将逻辑信号发送到传输路径的功能 在传输路径中具有一定量的信号衰减，在发送侧产生包括四种或更多种信号电压的波形，使预加重量变为可变，并使缓冲器的导通电阻Rs保持恒定。 选择器电路1至选择器电路3位于缓冲器之前，反相器能够通过选择器逻辑选择要输入到缓冲器的信号，反转数据信号，并且预加重量和预加重数量通过一个 选择器逻辑的选择信号。

公开(公告)号：US5406198A

公开(公告)日：1995-04-11

申请号：US70113

申请日：1993-06-01

申请人： Ritsuro Orihashi ,  Kosuke Kendo ,  Yoshihiko Hayashi

发明人： Ritsuro Orihashi ,  Kosuke Kendo ,  Yoshihiko Hayashi

IPC分类号： G01R31/319 ,  G06F1/10 ,  H03K5/15 ,  G04F10/00

CPC分类号： G01R31/3191 ,  G01R31/31922 ,  G06F1/10 ,  H03K5/1504

摘要： In a digital circuitry apparatus in which clock distribution can be performed with high accuracy even in the case where variations in delay time are caused by variations in the apparatus operating condition, programmed input data set to delay circuits are corrected by a circuit portion for measuring the delay time of a phase shifting adjustment delay circuit with respect to variations in delay time caused by variations in the apparatus operating condition, a first arithmetic operation circuit for calculating the rate of variation on the basis of measured values, and a second arithmetic operation circuit for calculating the quantity of variation on the basis of the rate of variation.