公开(公告)号：US08680881B2

公开(公告)日：2014-03-25

申请号：US13044717

申请日：2011-03-10

申请人： Yutaka Uematsu ,  Hideki Osaka ,  Satoshi Nakamura ,  Satoshi Muraoka ,  Mitsuaki Katagiri ,  Ken Iwakura ,  Yukitoshi Hirose

发明人： Yutaka Uematsu ,  Hideki Osaka ,  Satoshi Nakamura ,  Satoshi Muraoka ,  Mitsuaki Katagiri ,  Ken Iwakura ,  Yukitoshi Hirose

IPC分类号： G01R31/00

CPC分类号： G01R31/2889

摘要： An interposer to be mounted with an integrated circuit to be a test object is provided with a switch and a probe to detect an electric current corresponding to individual terminals of the integrated circuit. A test pattern signal is then inputted to the integrated circuit through a test substrate as a switch that is connected to a power supply terminal of the integrated circuit and that is turned off. If the integrated circuit normally operates and the current values of all the terminals of the integrated circuit are within a tolerance, the power supply terminal connected to the turned-off switch is identified as a terminal that may be removed.

摘要翻译： 安装有作为测试对象的集成电路的插入器设置有用于检测与集成电路的各个端子相对应的电流的开关和探头。 然后，通过作为与集成电路的电源端子连接并断开的开关的测试基板将测试图形信号输入到集成电路。 如果集成电路正常工作，并且集成电路的所有端子的电流值都在容差内，则连接到关断开关的电源端子被识别为可以被去除的端子。

公开(公告)号：US20110215830A1

公开(公告)日：2011-09-08

申请号：US13106926

申请日：2011-05-13

申请人： Satoshi MURAOKA ,  Norio Chujo ,  Ritsuro Orihashi

发明人： Satoshi MURAOKA ,  Norio Chujo ,  Ritsuro Orihashi

IPC分类号： H03K19/003

CPC分类号： H03K19/018521

摘要： An output buffer includes inverters, a delay circuit for delaying an input signal, buffers and switches. The output buffer transmits a logic signal to a transmission path and, in accordance with an amount of signal attenuation in the transmission path, creates a waveform including four or more kinds of signal voltages. The buffers are redundantly connected in parallel, and the number of buffers concurrently turn ON is controlled by respective switches provided in series with output resistors of the buffers. By selecting the buffers of switches which are turned ON, the preemphasis amount and a number of preemphasis taps are adjusted through a selector logic selection signal so that the preemphasis amount is made variable and the ON resistance of the buffers is made constant.

摘要翻译： 输出缓冲器包括反相器，用于延迟输入信号的延迟电路，缓冲器和开关。 输出缓冲器将逻辑信号发送到传输路径，并且根据传输路径中的信号衰减量产生包括四种或更多种信号电压的波形。 缓冲器并联冗余连接，同时导通的缓冲器的数量由与缓冲器的输出电阻器串联提供的相应开关控制。 通过选择接通的开关的缓冲器，通过选择器逻辑选择信号调整预加重量和预加重抽头数，使预加重量变为可变，并使缓冲器的导通电阻保持恒定。

公开(公告)号：US20100219856A1

公开(公告)日：2010-09-02

申请号：US12716796

申请日：2010-03-03

申请人： Satoshi MURAOKA ,  Norio Chujo ,  Ritsuro Orihashi

发明人： Satoshi MURAOKA ,  Norio Chujo ,  Ritsuro Orihashi

IPC分类号： H03K19/003 ,  H03K19/094

CPC分类号： H03K19/018521

摘要： In an output buffer circuit including Inverter 1 to Inverter 3, Delay Circuit 1 to Delay Circuit 3 for delaying an input signal for a specific time, Buffer 1 to Buffer 3, and a function for transmitting a logic signal to a transmission path and in accordance with an amount of signal attenuation in the transmission path, creating at a transmission side a waveform including four or more kinds of signal voltages, the preemphasis amount is made variable and the ON resistance Rs of the buffer is made constant. Selector circuit 1 to Selector circuit 3 are situated before the buffers, the inverter, capable of selecting through selector logic a signal to be inputted to the buffer, inverts a data signal, and the preemphasis amount and the number of preemphasis taps are adjusted through a selection signal for the selector logic.

摘要翻译： 在包括变频器1至变频器3的输出缓冲电路中，延迟电路1至延迟电路3用于将输入信号延迟特定时间，缓冲器1至缓冲器3，以及用于将逻辑信号发送到传输路径的功能 在传输路径中具有一定量的信号衰减，在发送侧产生包括四种或更多种信号电压的波形，使预加重量变为可变，并使缓冲器的导通电阻Rs保持恒定。 选择器电路1至选择器电路3位于缓冲器之前，反相器能够通过选择器逻辑选择要输入到缓冲器的信号，反转数据信号，并且预加重量和预加重数量通过一个 选择器逻辑的选择信号。

公开(公告)号：US20130307582A1

公开(公告)日：2013-11-21

申请号：US13512465

申请日：2012-05-16

申请人： Yasuhiro Ikeda ,  Yutaka Uematsu ,  Satoshi Muraoka

发明人： Yasuhiro Ikeda ,  Yutaka Uematsu ,  Satoshi Muraoka

IPC分类号： H03K17/16

CPC分类号： G11C7/10 ,  G11C7/1057 ,  G11C7/1084

摘要： To suppress power consumption and enhance signal quality as compared with the case where first and second semiconductor elements are terminated only by on-chip input termination resistor circuits. A first semiconductor element with a switching function and a second semiconductor element with a switching function are connected to each other with a substrate interconnection, and a resistor element is connected in parallel with the substrate interconnection. The resistor element is placed at an arbitrary position or a branch point on the signal interconnection.

摘要翻译： 与第一和第二半导体元件仅由片上输入终端电阻电路端接的情况相比，抑制功耗和提高信号质量。 具有开关功能的第一半导体元件和具有开关功能的第二半导体元件通过衬底互连彼此连接，并且电阻元件与衬底互连并联连接。 电阻元件放置在信号互连的任意位置或分支点处。

公开(公告)号：US20120262885A1

公开(公告)日：2012-10-18

申请号：US13358540

申请日：2012-01-26

申请人： Yasuhiro IKEDA ,  Yutaka Uematsu ,  Satoshi Muraoka

发明人： Yasuhiro IKEDA ,  Yutaka Uematsu ,  Satoshi Muraoka

IPC分类号： H05K1/18

CPC分类号： H05K1/0243 ,  H05K1/0251 ,  H05K1/115 ,  H05K2201/09227 ,  H05K2201/09772 ,  H05K2201/10545 ,  H05K2201/10689

摘要： Provided is a signal transfer circuit which uses a low cost circuit board with a high packing density but is capable of reducing a crosstalk noise between signal lines and also reducing a reflection noise due to a stub. A signal transfer circuit of the present invention is configured such that lead terminals of electronic components and through-hole vias are connected to each other by surface wirings, respectively, to allow no branching from the middle of the through-hole vias. Further, first wirings connecting a first electronic component are each arranged between a corresponding pair of second wirings connecting a second electronic component, and signals are transmitted through the first wirings and the second wirings by interleaved transmission.

摘要翻译： 提供了一种使用具有高包装密度的低成本电路板的信号传输电路，但是能够减少信号线之间的串扰噪声并且还减少由于短截线引起的反射噪声。 本发明的信号传输电路被配置为使得电子部件和通孔过孔的引线端子分别通过表面布线彼此连接，以便不允许从通孔过孔的中间分支。 此外，连接第一电子部件的第一布线分别布置在连接第二电子部件的相应的一对第二布线之间，并且信号通过交错传输通过第一布线和第二布线传输。

公开(公告)号：US20120194304A1

公开(公告)日：2012-08-02

申请号：US13354436

申请日：2012-01-20

申请人： Satoshi MURAOKA

发明人： Satoshi MURAOKA

IPC分类号： H04B3/14

CPC分类号： H04L25/03878 ,  H04B3/04 ,  H05K1/0233 ,  H05K1/0251 ,  H05K2201/086

摘要： An equalizer circuit includes a passive equalizer having an inductor connected in parallel to a signal interconnection line, the inductor being made up of a conductor portion formed on a side face of a through-hole of a circuit board.

摘要翻译： 均衡器电路包括具有与信号互连线并联连接的电感器的无源均衡器，电感器由形成在电路板的通孔的侧面上的导体部分构成。

公开(公告)号：US07969197B2

公开(公告)日：2011-06-28

申请号：US12716796

申请日：2010-03-03

申请人： Satoshi Muraoka ,  Norio Chujo ,  Ritsuro Orihashi

发明人： Satoshi Muraoka ,  Norio Chujo ,  Ritsuro Orihashi

IPC分类号： H03K19/094

CPC分类号： H03K19/018521

摘要： An output buffer includes inverters, a delay circuit for delaying an input signal, buffers and switches. The output buffer transmits a logic signal to a transmission path and, in accordance with an amount of signal attenuation in the transmission path, creates a waveform including four or more kinds of signal voltages. The buffers are redundantly connected in parallel, and the number of buffers concurrently turn ON is controlled by respective switches provided in series with output resistors of the buffers. By selecting the buffers of switches which are turned ON, the preemphasis amount and a number of preemphasis taps are adjusted through a selector logic selection signal so that the preemphasis amount is made variable and the ON resistance of the buffers is made constant.

摘要翻译： 输出缓冲器包括反相器，用于延迟输入信号的延迟电路，缓冲器和开关。 输出缓冲器将逻辑信号发送到传输路径，并且根据传输路径中的信号衰减量产生包括四种或更多种信号电压的波形。 缓冲器并联冗余连接，同时导通的缓冲器的数量由与缓冲器的输出电阻器串联提供的相应开关控制。 通过选择接通的开关的缓冲器，通过选择器逻辑选择信号调整预加重量和预加重抽头数，使预加重量变为可变，并使缓冲器的导通电阻保持恒定。

公开(公告)号：US20080265944A1

公开(公告)日：2008-10-30

申请号：US11686560

申请日：2007-03-15

申请人： SATOSHI MURAOKA ,  Norio Chujo ,  Ritsuro Orihashi

发明人： SATOSHI MURAOKA ,  Norio Chujo ,  Ritsuro Orihashi

IPC分类号： H03K19/0185 ,  H03K19/0175

CPC分类号： H03K19/018521

摘要： In an output buffer circuit including Inverter 1 to Inverter 3, Delay Circuit 1 to Delay Circuit 3 for delaying an input signal for a specific time, Buffer 1 to Buffer 3, and a function for transmitting a logic signal to a transmission path and in accordance with an amount of signal attenuation in the transmission path, creating at a transmission side a waveform including four or more kinds of signal voltages, the preemphasis amount is made variable and the ON resistance Rs of the buffer is made constant. Selector circuit 1 to Selector circuit 3 are situated before the buffers, the inverter, capable of selecting through selector logic a signal to be inputted to the buffer, inverts a data signal, and the preemphasis amount and the number of preemphasis taps are adjusted through a selection signal for the selector logic.

摘要翻译： 在包括变频器1至变频器3的输出缓冲电路中，延迟电路1至延迟电路3用于将输入信号延迟特定时间，缓冲器1至缓冲器3，以及用于将逻辑信号发送到传输路径的功能 在传输路径中具有一定量的信号衰减，在发送侧产生包括四种或更多种信号电压的波形，使预加重量变为可变，并使缓冲器的导通电阻Rs保持恒定。 选择器电路1至选择器电路3位于缓冲器之前，反相器能够通过选择器逻辑选择要输入到缓冲器的信号，反转数据信号，并且预加重量和预加重数量通过一个 选择器逻辑的选择信号。

公开(公告)号：US06993633B1

公开(公告)日：2006-01-31

申请号：US09628718

申请日：2000-07-28

申请人： Tadayuki Sakakibara ,  Isao Ohara ,  Hideya Akashi ,  Yuji Tsushima ,  Satoshi Muraoka

发明人： Tadayuki Sakakibara ,  Isao Ohara ,  Hideya Akashi ,  Yuji Tsushima ,  Satoshi Muraoka

IPC分类号： G06F9/38

CPC分类号： G06F12/0862 ,  G06F12/084

摘要： A cache data control system and method for a computer system in which in a memory read processing, a coherent controller issues an advanced speculative read request for (speculatively) reading data from a cache data section in advance to a cache data controller, before reading a cache tag from a cache tag section and conducting cache hit check. If a cache hit has occurred, the cache data controller returns the data subjected to speculative reading as response data, at the time when the cache data controller has received a read request issued by the coherent controller.

摘要翻译： 一种用于计算机系统的高速缓存数据控制系统和方法，其中在存储器读取处理中，相干控制器在读取之前向高速缓存数据控制器发送用于（推测性地）将数据从高速缓存数据部分读取的高级推测性读请求 缓存标签从缓存标签部分进行缓存命中检查。 如果发生了高速缓存命中，则高速缓存数据控制器接收到由相干控制器发出的读请求时，将经过推测读取的数据作为响应数据返回。

公开(公告)号：US20160188511A1

公开(公告)日：2016-06-30

申请号：US14423769

申请日：2014-04-25

申请人： Satoshi MURAOKA ,  Keisuke HATASAKI ,  Mutsumi HOSOYA ,  Yasunori KANEDA ,  Toshihiro ISHIKI

发明人： Satoshi MURAOKA ,  Keisuke HATASAKI ,  Mutsumi HOSOYA ,  Yasunori KANEDA ,  Toshihiro ISHIKI

IPC分类号： G06F13/364 ,  G06F13/40 ,  G06F13/42

CPC分类号： G06F13/364 ,  G06F13/4022 ,  G06F13/4282

摘要： A computer system includes a switch having a plurality of ports, a plurality of devices coupled to the plurality of ports, and a management system coupled to at least one of the plurality of devices and the switch. The coupling between the plurality of devices and the switch is a communication interface in which the number of master devices capable of existing in the same space is defined. The management system collects device coupling data of each of the plurality of devices coupled to the switch. Each of the device coupling data includes an ID of a port to which the device is coupled and information representing an attribute indicating whether the device is a master or a slave. The management system determines a coupling configuration on the basis of the plurality of the collected device coupling data and a communication interface protocol and, configures, to the switch, coupling information that is information in accordance with the determined coupling configuration.

摘要翻译： 计算机系统包括具有多个端口的交换机，耦合到多个端口的多个设备，以及耦合到多个设备和交换机中的至少一个的管理系统。 多个设备和交换机之间的耦合是其中能够存在于相同空间中的主设备的数量被定义的通信接口。 管理系统收集耦合到交换机的多个设备中的每一个的设备耦合数据。 每个设备耦合数据包括设备耦合到的端口的ID和表示设备是主设备还是从设备的属性的信息。 管理系统基于多个收集的设备耦合数据和通信接口协议来确定耦合配置，并且根据所确定的耦合配置向交换机配置作为信息的耦合信息。