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1.发明申请公开(公告)号：US20090122305A1
公开(公告)日：2009-05-14
申请号：US12266663
申请日：2008-11-07
IPC分类号： G01N21/88
CPC分类号： G01N21/9501 , G01N21/8851 , G01N21/94
摘要： In a foreign matter inspection apparatus for a semiconductor wafer, a PMT which detects reflection light, an amplifier which amplifies a signal detected by the PMT and in which response characteristics of amplification are controlled by a control signal, an A/D converter which converts the signal amplified by the amplifier into a predetermined code and outputs the code, a control circuit which generates a control signal based on information of the semiconductor wafer having a correlation with the reflection light, and a data processing circuit which detects a foreign matter on the semiconductor wafer based on the code output from the A/D converter are provided.
摘要翻译： 在半导体晶片的异物检查装置中，检测反射光的PMT，放大由PMT检测出的信号的放大器，其中由控制信号控制放大的响应特性的放大器，A / D转换器 信号由放大器放大成预定码并输出该代码;基于与反射光相关的半导体晶片的信息产生控制信号的控制电路;以及检测半导体上的异物的数据处理电路 提供了基于A / D转换器的代码输出的晶片。
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2.发明授权公开(公告)号：US07276900B2
公开(公告)日：2007-10-02
申请号：US11272861
申请日：2005-11-15
IPC分类号： G01R33/12
CPC分类号： G11B5/455 , G11B5/4555 , G11B20/1816 , G11B27/36 , G11B2005/001 , G11B2005/0013
摘要： A magnetic characteristic inspecting apparatus including a plurality of disk rotating devices or a plurality of magnetic heads include a unit for switching output signals of write signal production units or allocating the output signals to the magnetic heads, a unit for switching signals read from the magnetic heads or allocating the read signals to measurement resources, and a unit for selecting any of the disk rotating devices synchronously with which the measurement resources will perform measurement. The write signal production units and measurement resources are shared among inspections of the plurality of disk rotating devices or the plurality of heads.
摘要翻译： 包括多个盘旋转装置或多个磁头的磁特性检查装置包括用于切换写入信号产生单元的输出信号或将输出信号分配给磁头的单元，用于切换从磁头读取的信号的单元 或将读取信号分配给测量资源，以及用于选择与测量资源将执行测量同步的任何盘旋转设备的单元。 写入信号生成单元和测量资源在多个盘旋转装置或多个头的检查之间共享。
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公开(公告)号：US20060289739A1
公开(公告)日：2006-12-28
申请号：US11431656
申请日：2006-05-11
IPC分类号： H01J49/00
CPC分类号： H01J49/40 , H01J49/0036
摘要： The present invention relates to a data processing device for mass spectrometry, in which measurements are performed in a high dynamic range without causing an overrange in an A/D converter in any TOF scan. A data acquisition circuit of a mass spectrometer includes an amplitude value computing circuit which measures and stores a maximum amplitude value of an ion detection signal, a gain control circuit for determining and setting a gain amount for the next measurement, and others. From the immediately preceding TOF scan data or TOF scan data plural times before, the maximum amplitude value of the ion detection signal is extracted. Then, before the next TOF scan, an optimum gain amount is determined based on the extracted maximum amplitude value to adjust the gain of the input signal, and the ion signal is sampled in the A/D converter.
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4.发明申请公开(公告)号：US20060132122A1
公开(公告)日：2006-06-22
申请号：US11272861
申请日：2005-11-15
IPC分类号： G01R33/12
CPC分类号： G11B5/455 , G11B5/4555 , G11B20/1816 , G11B27/36 , G11B2005/001 , G11B2005/0013
摘要： A magnetic characteristic inspecting apparatus including a plurality of disk rotating devices or a plurality of magnetic heads include a unit for switching output signals of write signal production units or allocating the output signals to the magnetic heads, a unit for switching signals read from the magnetic heads or allocating the read signals to measurement resources, and a unit for selecting any of the disk rotating devices synchronously with which the measurement resources will perform measurement. The write signal production units and measurement resources are shared among inspections of the plurality of disk rotating devices or the plurality of heads.
摘要翻译： 包括多个盘旋转装置或多个磁头的磁特性检查装置包括用于切换写入信号产生单元的输出信号或将输出信号分配给磁头的单元，用于切换从磁头读取的信号的单元 或将读取信号分配给测量资源，以及用于选择与测量资源将执行测量同步的任何盘旋转设备的单元。 写入信号生成单元和测量资源在多个盘旋转装置或多个头的检查之间共享。
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5.发明申请OUTPUT BUFFER CIRCUIT AND DIFFERENTIAL OUTPUT BUFFER CIRCUIT, AND TRANSMISSION METHOD 有权输出缓冲电路和差分输出缓冲电路及传输方式公开(公告)号：US20110215830A1
公开(公告)日：2011-09-08
申请号：US13106926
申请日：2011-05-13
申请人： Satoshi MURAOKA , Norio Chujo , Ritsuro Orihashi
发明人： Satoshi MURAOKA , Norio Chujo , Ritsuro Orihashi
IPC分类号： H03K19/003
CPC分类号： H03K19/018521
摘要： An output buffer includes inverters, a delay circuit for delaying an input signal, buffers and switches. The output buffer transmits a logic signal to a transmission path and, in accordance with an amount of signal attenuation in the transmission path, creates a waveform including four or more kinds of signal voltages. The buffers are redundantly connected in parallel, and the number of buffers concurrently turn ON is controlled by respective switches provided in series with output resistors of the buffers. By selecting the buffers of switches which are turned ON, the preemphasis amount and a number of preemphasis taps are adjusted through a selector logic selection signal so that the preemphasis amount is made variable and the ON resistance of the buffers is made constant.
摘要翻译： 输出缓冲器包括反相器，用于延迟输入信号的延迟电路，缓冲器和开关。 输出缓冲器将逻辑信号发送到传输路径，并且根据传输路径中的信号衰减量产生包括四种或更多种信号电压的波形。 缓冲器并联冗余连接，同时导通的缓冲器的数量由与缓冲器的输出电阻器串联提供的相应开关控制。 通过选择接通的开关的缓冲器，通过选择器逻辑选择信号调整预加重量和预加重抽头数，使预加重量变为可变，并使缓冲器的导通电阻保持恒定。
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公开(公告)号：US20110192970A1
公开(公告)日：2011-08-11
申请号：US13090009
申请日：2011-04-19
IPC分类号： H01J49/40
CPC分类号： H01J49/0036 , H01J49/40
摘要： For the achievement of data transfer time reduction, removal of noise data, and analytical efficiency improvement in an ADC data processing function of a time-of-flight mass spectrometer, the mass spectrometer comprises a data acquisition circuit including: an ND converter; a signal intensity addition memory that stores data of ion signals such as a time range and the number of measurements and performs an addition process; a voltage value frequency addition memory that performs an addition process of frequencies of voltage values of the predetermined time range and the number of measurements and stores addition results; a threshold level computation circuit that computes a predetermined threshold level from the results in the memory; a compression memory that extracts only data exceeding the threshold level from the data in the signal intensity addition memory; and a counter that controls a measurement time for data acquisition and the operation of each circuit.
摘要翻译： 为了实现数据传输时间的减少，噪声数据的去除以及飞行时间质谱仪的ADC数据处理功能的分析效率改进，质谱仪包括数据采集电路，包括：ND转换器; 信号强度相加存储器，其存储诸如时间范围和测量次数的离子信号的数据，并执行加法处理; 电压值频率相加存储器，其执行预定时间范围的电压值的频率和测量次数的加法处理，并存储加法结果; 阈值电平计算电路，用于根据存储器中的结果计算预定的阈值电平; 压缩存储器，其从信号强度相加存储器中的数据中仅提取超过阈值电平的数据; 以及控制数据采集和每个电路的操作的测量时间的计数器。
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7.发明申请OUTPUT BUFFER CIRCUIT AND DIFFERENTIAL OUTPUT BUFFER CIRCUIT, AND TRANSMISSION METHOD 有权输出缓冲电路和差分输出缓冲电路及传输方式公开(公告)号：US20100219856A1
公开(公告)日：2010-09-02
申请号：US12716796
申请日：2010-03-03
申请人： Satoshi MURAOKA , Norio Chujo , Ritsuro Orihashi
发明人： Satoshi MURAOKA , Norio Chujo , Ritsuro Orihashi
IPC分类号： H03K19/003 , H03K19/094
CPC分类号： H03K19/018521
摘要： In an output buffer circuit including Inverter 1 to Inverter 3, Delay Circuit 1 to Delay Circuit 3 for delaying an input signal for a specific time, Buffer 1 to Buffer 3, and a function for transmitting a logic signal to a transmission path and in accordance with an amount of signal attenuation in the transmission path, creating at a transmission side a waveform including four or more kinds of signal voltages, the preemphasis amount is made variable and the ON resistance Rs of the buffer is made constant. Selector circuit 1 to Selector circuit 3 are situated before the buffers, the inverter, capable of selecting through selector logic a signal to be inputted to the buffer, inverts a data signal, and the preemphasis amount and the number of preemphasis taps are adjusted through a selection signal for the selector logic.
摘要翻译： 在包括变频器1至变频器3的输出缓冲电路中，延迟电路1至延迟电路3用于将输入信号延迟特定时间，缓冲器1至缓冲器3，以及用于将逻辑信号发送到传输路径的功能 在传输路径中具有一定量的信号衰减，在发送侧产生包括四种或更多种信号电压的波形，使预加重量变为可变，并使缓冲器的导通电阻Rs保持恒定。 选择器电路1至选择器电路3位于缓冲器之前，反相器能够通过选择器逻辑选择要输入到缓冲器的信号，反转数据信号，并且预加重量和预加重数量通过一个 选择器逻辑的选择信号。
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公开(公告)号：US07668027B2
公开(公告)日：2010-02-23
申请号：US11365492
申请日：2006-03-02
IPC分类号： G11C11/00
CPC分类号： G11C29/50 , G11C29/50012
摘要： In order to easily perform a timing test on a memory interface included in a semiconductor device so as to satisfy a restriction on latency, the present invention provides a semiconductor device with the memory interface including: a clock output terminal that outputs a clock signal associated with an operation of a memory connected to the memory interface; a command terminal that outputs a command signal associated with control of a state of the memory; a data terminal that exchanges a data signal with the memory; and a data strobe terminal that exchanges a data strobe signal for establishing the data signal. This semiconductor device includes a testing terminal that outputs in advance a signal for starting a test on the memory interface apart from the command signal.
摘要翻译： 为了容易地对包括在半导体器件中的存储器接口执行定时测试以满足对等待时间的限制，本发明提供一种具有存储器接口的半导体器件，包括：时钟输出端子，其输出与 连接到存储器接口的存储器的操作; 命令终端，其输出与所述存储器的状态的控制相关联的命令信号; 与存储器交换数据信号的数据终端; 以及数据选通端子，用于交换用于建立数据信号的数据选通信号。 该半导体器件包括测试端子，其预先输出用于在命令信号之外的存储器接口上开始测试的信号。
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公开(公告)号：US20070047345A1
公开(公告)日：2007-03-01
申请号：US11365492
申请日：2006-03-02
IPC分类号： G11C29/00
CPC分类号： G11C29/50 , G11C29/50012
摘要： In order to easily perform a timing test on a memory interface included in a semiconductor device so as to satisfy a restriction on latency, the present invention provides a semiconductor device with the memory interface including: a clock output terminal that outputs a clock signal associated with an operation of a memory connected to the memory interface; a command terminal that outputs a command signal associated with control of a state of the memory; a data terminal that exchanges a data signal with the memory; and a data strobe terminal that exchanges a data strobe signal for establishing the data signal. This semiconductor device includes a testing terminal that outputs in advance a signal for starting a test on the memory interface apart from the command signal.
摘要翻译： 为了容易地对包括在半导体器件中的存储器接口执行定时测试以满足对等待时间的限制，本发明提供一种具有存储器接口的半导体器件，包括：时钟输出端子，其输出与 连接到存储器接口的存储器的操作; 命令终端，其输出与所述存储器的状态的控制相关联的命令信号; 与存储器交换数据信号的数据终端; 以及数据选通端子，用于交换用于建立数据信号的数据选通信号。 该半导体器件包括测试端子，其预先输出用于在命令信号之外的存储器接口上开始测试的信号。
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公开(公告)号：US06697755B2
公开(公告)日：2004-02-24
申请号：US10159146
申请日：2002-05-31
IPC分类号： G01D1800
CPC分类号： G01R31/3193
摘要： In an odd side storage circuit, logical values of a decision subject signal HCMP are stored in first and second FFs respectively at decision edges LH and HL generated from odd-numbered edges of a decision edge EH. Logical values of a delayed decision subject signal HCMP′ are stored in third and fourth FFs. According to a selection signal generated by a selection signal generation circuit based on outputs of the third and fourth FFs, a first selector selects an output of the first or second FF. An even side storage circuit operates similarly at even-numbered edges. A second selector selects the odd and even side storage circuits alternately. The FFs in the odd and even side storage circuits are reset by a decision edge LH′ of the even side and the decision edge HL of the odd side, respectively.
摘要翻译： 在奇数侧存储电路中，决策对象信号HCMP的逻辑值分别存储在从判定边缘EH的奇数边缘产生的判定边缘LH和HL处的第一和第二FF中。 延迟决定对象信号HCMP'的逻辑值存储在第三和第四FF中。 根据由选择信号发生电路基于第三和第四FF的输出产生的选择信号，第一选择器选择第一或第二FF的输出。 偶数侧存储电路在偶数边缘类似地工作。 第二选择器交替地选择奇数和偶数侧存储电路。 奇数侧和偶数侧存储电路中的FF分别由奇数侧的判定边缘LH'和奇数侧的判定边缘HL复位。
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