公开(公告)号：US20090315117A1

公开(公告)日：2009-12-24

申请号：US12141314

申请日：2008-06-18

申请人： Thomas W. Dyer ,  Haining S. Yang

发明人： Thomas W. Dyer ,  Haining S. Yang

IPC分类号： H01L21/8238 ,  H01L27/092

CPC分类号： H01L21/823842 ,  H01L21/764 ,  H01L21/823864 ,  H01L21/823871 ,  H01L29/4966 ,  H01L29/517

摘要： Stress enhanced transistor devices and methods of fabricating the same are provided. In one embodiment, a transistor device comprises: a gate conductor disposed above a semiconductor substrate between a pair of dielectric spacers, wherein the semiconductor substrate comprises a channel region underneath the gate conductor and recessed regions on opposite sides of the channel region, wherein the recessed regions undercut the dielectric spacers to form undercut areas of the channel region; and epitaxial source and drain regions disposed in the recessed regions of the semiconductor substrate and extending laterally underneath the dielectric spacers into the undercut areas of the channel region.

摘要翻译： 提供了应力增强型晶体管器件及其制造方法。 在一个实施例中，晶体管器件包括：栅极导体，设置在一对电介质间隔物之间​​的半导体衬底之上，其中半导体衬底包括位于栅极导体下方的沟道区域和沟道区域相对侧上的凹陷区域， 区域覆盖电介质间隔物以形成通道区域的底切区域; 以及设置在半导体衬底的凹陷区域中的外延源极和漏极区域，并且在电介质间隔物的下方横向延伸到沟道区域的底切区域中。

公开(公告)号：US07569446B2

公开(公告)日：2009-08-04

申请号：US11761466

申请日：2007-06-12

申请人： Bruce B. Doris ,  Thomas W. Dyer ,  Haining S. Yang

发明人： Bruce B. Doris ,  Thomas W. Dyer ,  Haining S. Yang

IPC分类号： H01L21/8238

CPC分类号： H01L21/823878 ,  H01L21/28079 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/495 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

摘要： A complimentary metal oxide semiconductor and a method of manufacturing the same using a self-aligning process to form one of the stacks of device. The method includes depositing an oxide layer over a portion of a metal layer over an nFET region of a CMOS structure and etching the metal layer over a pFET region of the CMOS structure. The method further includes etching at the oxide layer over the nFET region and forming gate structures over the nFET region and pFET region.

摘要翻译： 互补的金属氧化物半导体及其制造方法使用自对准工艺来形成器件堆叠之一。 该方法包括在CMOS结构的nFET区域上的金属层的一部分上沉积氧化物层，并在CMOS结构的pFET区域上蚀刻金属层。 该方法还包括在nFET区域上的氧化物层处蚀刻并在nFET区域和pFET区域上形成栅极结构。

公开(公告)号：US08217470B2

公开(公告)日：2012-07-10

申请号：US12702682

申请日：2010-02-09

申请人： Xiangdong Chen ,  Brian J. Greene ,  Haining S. Yang

发明人： Xiangdong Chen ,  Brian J. Greene ,  Haining S. Yang

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7848 ,  H01L21/28194 ,  H01L29/1054 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66651

摘要： A field effect structure and a method for fabricating the field effect structure include a germanium containing channel interposed between a plurality of source and drain regions. The germanium containing channel is coplanar with the plurality of source and drain regions, and the germanium containing channel includes a germanium containing material having a germanium content greater than the germanium content of the plurality of source and drain regions.

摘要翻译： 场效应结构和用于制造场效应结构的方法包括介于多个源区和漏区之间的含锗通道。 含锗通道与多个源极和漏极区域共面，并且含锗沟道包括锗含量大于多个源极和漏极区的锗含量的含锗材料。

公开(公告)号：US20110175170A1

公开(公告)日：2011-07-21

申请号：US12691183

申请日：2010-01-21

申请人： Xinlin Wang ,  Xiangdong Chen ,  Haining S. Yang

发明人： Xinlin Wang ,  Xiangdong Chen ,  Haining S. Yang

IPC分类号： H01L29/66 ,  H01L21/8238

CPC分类号： H01L27/092 ,  H01L21/823462 ,  H01L21/823468 ,  H01L21/823857 ,  H01L21/823864 ,  H01L27/11 ,  H01L27/1104

摘要： An improved SRAM and fabrication method are disclosed. The method comprises use of a nitride layer to encapsulate PFETs and logic NFETs, protecting the gates of those devices from oxygen exposure. NFETs that are used in the SRAM cells are exposed to oxygen during the anneal process, which alters the effective work function of the gate metal, such that the threshold voltage is increased, without the need for increasing the dopant concentration, which can adversely affect issues such as mismatch due to random dopant fluctuation, GIDL and junction leakage.

摘要翻译： 公开了一种改进的SRAM和制造方法。 该方法包括使用氮化物层来封装PFET和逻辑NFET，保护这些器件的栅极免受氧气暴露。 用于SRAM单元中的NFET在退火过程中暴露于氧气，这改变了栅极金属的有效功函数，使得阈值电压增加，而不需要增加掺杂剂浓度，这可能不利地影响问题 例如由于随机掺杂剂波动，GIDL和结泄漏引起的失配。

公开(公告)号：US07935993B2

公开(公告)日：2011-05-03

申请号：US12643482

申请日：2009-12-21

申请人： Xiangdong Chen ,  Haining S. Yang

发明人： Xiangdong Chen ,  Haining S. Yang

IPC分类号： H01L29/76

CPC分类号： H01L21/823807 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843

摘要： A method for making a semiconductor device structure, includes: providing a substrate; forming on the substrate: a first layer below and second layers on a gate with spacers, source and drain regions adjacent to the gate, silicides on the gate and source and drain regions; disposing a stress layer over the structure resulting from the forming step; disposing an insulating layer over the stress layer; removing portions of the insulating layer to expose a top surface of the stress layer; removing the top surface and other portions of the stress layer and portions of the spacers to form a trench, and then disposing a suitable stress material into the trench.

摘要翻译： 一种制造半导体器件结构的方法，包括：提供衬底; 在衬底上形成：在栅极上的第一层和栅极上的第二层，具有间隔物，与栅极相邻的源极和漏极区域，栅极上的硅化物和源极和漏极区域; 在由成形步骤导致的结构上设置应力层; 在应力层上设置绝缘层; 去除绝缘层的部分以暴露应力层的顶表面; 去除应力层的顶表面和其它部分和间隔物的部分以形成沟槽，然后将合适的应力材料设置到沟槽中。

公开(公告)号：US07361539B2

公开(公告)日：2008-04-22

申请号：US11383560

申请日：2006-05-16

申请人： Xiangdong Chen ,  Haining S. Yang

发明人： Xiangdong Chen ,  Haining S. Yang

IPC分类号： H01L21/336 ,  H01L21/8234

CPC分类号： H01L21/823807 ,  H01L29/7842

摘要： A semiconductor device structure is provided which includes a first field effect transistor (“FET”) having a first channel region, a first source region, a first drain region and a first gate conductor overlying the first channel region. A second FET is included which has a second channel region, a second source region, a second drain region and a second gate conductor overlying the second channel region. The first and second gate conductors are portions of a single elongated conductive member extending over both the first and second channel regions. A first stressed film overlies the first FET, the first stressed film applying a stress having a first value to the first channel region. A second stressed film overlies the second FET, the second stressed film applying a stress having a second value to the second channel region. The second value is substantially different from the first value. In addition, the first and second stressed films abut each other at a common boundary and present a substantially co-planar major surface at the common boundary.

摘要翻译： 提供一种半导体器件结构，其包括第一场效应晶体管（“FET”），其具有第一沟道区，第一源极区，第一漏极区和覆盖第一沟道区的第一栅极导体。 包括第二FET，其具有覆盖第二沟道区的第二沟道区，第二源极区，第二漏极区和第二栅极导体。 第一和第二栅极导体是在第一和第二沟道区两者上延伸的单个细长导电构件的部分。 第一应力膜覆盖第一FET，第一应力膜将具有第一值的应力施加到第一沟道区。 第二应力膜覆盖第二FET，第二应力膜向第二沟道区施加具有第二值的应力。 第二个值与第一个值大不相同。 此外，第一和第二应力膜在共同边界处彼此邻接并且在共同边界处呈现基本上共平面的主表面。

公开(公告)号：US08697521B2

公开(公告)日：2014-04-15

申请号：US12691183

申请日：2010-01-21

申请人： Xinlin Wang ,  Xiangdong Chen ,  Haining S. Yang

发明人： Xinlin Wang ,  Xiangdong Chen ,  Haining S. Yang

IPC分类号： H01L27/092

CPC分类号： H01L27/092 ,  H01L21/823462 ,  H01L21/823468 ,  H01L21/823857 ,  H01L21/823864 ,  H01L27/11 ,  H01L27/1104

摘要： An improved SRAM and fabrication method are disclosed. The method comprises use of a nitride layer to encapsulate PFETs and logic NFETs, protecting the gates of those devices from oxygen exposure. NFETs that are used in the SRAM cells are exposed to oxygen during the anneal process, which alters the effective work function of the gate metal, such that the threshold voltage is increased, without the need for increasing the dopant concentration, which can adversely affect issues such as mismatch due to random dopant fluctuation, GIDL and junction leakage.

摘要翻译： 公开了一种改进的SRAM和制造方法。 该方法包括使用氮化物层来封装PFET和逻辑NFET，保护这些器件的栅极免受氧气暴露。 用于SRAM单元中的NFET在退火过程中暴露于氧气，这改变了栅极金属的有效功函数，使得阈值电压增加，而不需要增加掺杂剂浓度，这可能不利地影响问题 例如由于随机掺杂剂波动，GIDL和结泄漏引起的失配。

公开(公告)号：US07960223B2

公开(公告)日：2011-06-14

申请号：US12139764

申请日：2008-06-16

申请人： Xiangdong Chen ,  Haining S. Yang

发明人： Xiangdong Chen ,  Haining S. Yang

IPC分类号： H01L21/8238

CPC分类号： H01L21/823835 ,  H01L21/823807 ,  H01L29/7843

摘要： The present invention provides a semiconducting device including a substrate including a semiconducting surface having an n-type device in a first device region and a p-type device in a second device region, the n-type device including a first gate structure present overlying a portion of the semiconducting surface in the first device region including a first work function metal semiconductor alloy in the semiconducting surface adjacent to the portion of the semiconducting surface underlying the gate structure, and a first type strain inducing layer present overlying the first device region; and a p-type device including a second gate structure present overlying a portion of the semiconducting surface in the second device region including a second work function metal semiconductor alloy in the semiconducting surface adjacent to the portion of the semiconducting surface underlying the gate structure, and a second type strain inducing layer present overlying the second device region.

摘要翻译： 本发明提供了一种半导体器件，其包括：衬底，其包括在第一器件区域中具有n型器件的半导体表面和在第二器件区域中的p型器件，所述n型器件包括第一栅极结构， 所述第一器件区域中的所述半导体表面的部分包括与所述栅极结构下方的所述半导体表面的部分相邻的所述半导体表面中的第一功函数金属半导体合金，以及存在于所述第一器件区域上方的第一类型应变诱导层; 以及包括第二栅极结构的p型器件，所述第二栅极结构覆盖所述第二器件区域中的所述半导体表面的一部分，所述第二栅极结构包括与所述栅极结构的所述半导体表面的所述部分相邻的所述半导体表面中的第二功函数金属半导体合金， 存在覆盖在第二器件区域上的第二类型应变诱导层。

公开(公告)号：US07947557B2

公开(公告)日：2011-05-24

申请号：US11931341

申请日：2007-10-31

申请人： Xiangdong Chen ,  Haining S. Yang

发明人： Xiangdong Chen ,  Haining S. Yang

IPC分类号： H01L21/336

CPC分类号： H01L29/78 ,  H01L29/165 ,  H01L29/66356 ,  H01L29/7391

摘要： The present invention relates to a heterojunction tunneling effect transistor (TFET), which comprises spaced apart source and drain regions with a channel region located therebetween and a gate stack located over the channel region. The drain region comprises a first semiconductor material and is doped with a first dopant species of a first conductivity type. The source region comprises a second, different semiconductor material and is doped with a second dopant species of a second, different conductivity type. The gate stack comprises at least a gate dielectric and a gate conductor. When the heterojunction TFET is an n-channel TFET, the drain region comprises n-doped silicon, while the source region comprises p-doped silicon germanium.

摘要翻译： 本发明涉及异质结隧道效应晶体管（TFET），其包括间隔开的源极和漏极区，其中位于其间的沟道区和位于沟道区上方的栅极叠层。 漏极区域包括第一半导体材料并且掺杂有第一导电类型的第一掺杂物种类。 源区包括第二不同的半导体材料，并且掺杂有第二不同导电类型的第二掺杂物种。 栅极堆叠至少包括栅极电介质和栅极导体。 当异质结TFET是n沟道TFET时，漏极区域包括n掺杂的硅，而源极区域包括p掺杂的硅锗。

公开(公告)号：US07943454B2

公开(公告)日：2011-05-17

申请号：US12080016

申请日：2008-03-31

申请人： Xiangdong Chen ,  Haining S. Yang

发明人： Xiangdong Chen ,  Haining S. Yang

IPC分类号： H01L21/8238

CPC分类号： H01L21/823807 ,  H01L29/7842

摘要： A semiconductor device structure is provided which includes a first field effect transistor (“FET”) having a first channel region, a first source region, a first drain region and a first gate conductor overlying the first channel region. A second FET is included which has a second channel region, a second source region, a second drain region and a second gate conductor overlying the second channel region. The first and second gate conductors can be portions of a single elongated conductive member extending over both the first and second channel regions. A first stressed film may overlie the first FET and the first stressed film may apply a stress having a first value to the first channel region. A second stressed film may overlie the second FET and the second stressed film may apply a stress having a second value to the second channel region. The second value is substantially different from the first value. The first and second stressed films can abut each other at a common boundary and present a substantially co-planar major surface at the common boundary.

摘要翻译： 提供一种半导体器件结构，其包括第一场效应晶体管（“FET”），其具有第一沟道区，第一源极区，第一漏极区和覆盖第一沟道区的第一栅极导体。 包括第二FET，其具有覆盖第二沟道区的第二沟道区，第二源极区，第二漏极区和第二栅极导体。 第一和第二栅极导体可以是在第一和第二通道区域上延伸的单个细长导电构件的部分。 第一应力膜可以覆盖第一FET，并且第一应力膜可以向第一沟道区域施加具有第一值的应力。 第二应力膜可以覆盖第二FET，并且第二应力膜可以向第二沟道区域施加具有第二值的应力。 第二个值与第一个值大不相同。 第一和第二应力膜可以在共同的边界彼此邻接并且在公共边界处呈现基本上共平面的主表面。