公开(公告)号：US20220302018A1

公开(公告)日：2022-09-22

申请号：US17308270

申请日：2021-05-05

Applicant: Microchip Technology Incorporated

Inventor： Yaojian Leng

IPC: H01L23/522 ,  H01L49/02 ,  H01L21/768

Abstract: An integrated circuit structure includes a metal-insulator-metal (MIM) capacitor and a thin-film resistor (TFR) formed concurrently, using components of shared material layers. A first metal layer may be patterned to form lower components of an interconnect structure, MIM capacitor, and TFR, and a second metal layer may be patterned to form upper components of the interconnect structure, MIM capacitor, and TFR. A via layer may be deposited to form interconnect vias, a cup-shaped bottom electrode component of the MIM capacitor, and a pair of TFR contact vias for the TFR. An insulator layer may be patterned to form both an insulator for the MIM capacitor and an insulator cap over the TFR element.

公开(公告)号：US20220271117A1

公开(公告)日：2022-08-25

申请号：US17233285

申请日：2021-04-16

Applicant: Microchip Technology Incorporated

Inventor： Yaojian Leng

IPC: H01L49/02 ,  H01L23/532 ,  H01L21/768 ,  H01C7/00

Abstract: A thin-film resistor (TFR) module is formed in an integrated circuit device. The TFR module includes a pair of metal TFR heads (e.g., copper damascene trench structures), a TFR element formed directly on the metal TFR heads to define a conductive path between the pair of TFR heads through the TFR element, and TFR contacts connected to the TFR heads. The TFR heads may be formed in a metal interconnect layer, along with various interconnect elements of the integrated circuit device. The TFR element may be formed by depositing and patterning a TFR element/diffusion barrier layer over the TFR heads and interconnect elements formed in the metal interconnect layer. The TFR element may be formed from a material that also provides a barrier against metal diffusion (e.g., copper diffusion) from each metal TFR head and interconnect element. For example, the TFR element may be formed from tantalum nitride (TaN).

公开(公告)号：US20220069069A1

公开(公告)日：2022-03-03

申请号：US17155431

申请日：2021-01-22

Applicant: Microchip Technology Incorporated

Inventor： Yaojian Leng ,  Justin Sato

IPC: H01L49/02 ,  H01L23/522

Abstract: A three-dimensional metal-insulator-metal (MIM) capacitor is formed in an integrated circuit structure. The 3D MIM capacitor may include a bottom conductor including a bottom plate portion (e.g., formed in a metal interconnect layer) and vertically-extending sidewall portions extending from the bottom plate portion. An insulator layer is formed on the bottom plate portion and the vertically extending sidewall portions of the bottom conductor. A top conductor is formed over the insulating layer, such that the top conductor is capacitively coupled to both the bottom plate portion and the vertically extending sidewall portions of the bottom conductor, to thereby define an increased area of capacitive coupling between the top and bottom conductors. The vertically extending sidewall portions of the bottom conductor may be formed in a single metal layer or by components of multiple metal layers.

公开(公告)号：US20210335627A1

公开(公告)日：2021-10-28

申请号：US17111973

申请日：2020-12-04

Applicant: Microchip Technology Incorporated

Inventor： Justin Sato ,  Yaojian Leng ,  Bomy Chen ,  Chris Sundahl

IPC: H01L21/48 ,  H01L23/498 ,  H01L21/56

Abstract: Methods are provided for forming an integrated circuit (IC) package interposer configured for back-side attachment. A porous silicon double layer is formed on a bulk silicon wafer, e.g., using a controlled anodization, the porous silicon double layer including two porous silicon layers having different porosities. An interposer is formed over the porous silicon double layer, the interposer including back-side contacts, front-side contacts, and conductive structures (e.g., vias and metal interconnect) extending through the interposer to connect selected back-side contacts with selected front-side contacts. The structure is then split at the interface between the first and second porous silicon layers of the silicon double layer, and the interposer including the second porous silicon layers is inverted and etched to remove the second silicon layer and expose the back-side contacts, such that the exposed back-side contacts can be used for back-side attachment of the interposer to a package substrate or other structure.

公开(公告)号：US11101208B2

公开(公告)日：2021-08-24

申请号：US16741921

申请日：2020-01-14

Applicant: Microchip Technology Incorporated

Inventor： Yaojian Leng

IPC: H01L23/522 ,  H01L49/02 ,  H01L23/532 ,  H01L23/48 ,  H01L23/00

Abstract: A process of forming a metal-insulator-metal (MIM) capacitor may be incorporated into a process of forming metal bond pads connected directly to a top metal interconnect layer (e.g., Cu MTOP). The MIM capacitor may include a dielectric layer formed between a bottom plate defined by the Cu MTOP and a top plate comprising an extension of, or connected directly to, a metal bond pad formed above the Cu MTOP. The process of forming the MIM capacitor may include etching an opening in a passivation layer formed over the Cu MTOP to expose a top surface of the Cu MTOP, forming a dielectric layer extending into the passivation layer opening and onto the exposed Cu MTOP surface, removing portions of the dielectric layer to define a capacitor dielectric, and depositing bond pad metal extending into the passivation layer opening and onto the capacitor dielectric, to define the MIM capacitor top plate.

公开(公告)号：US20210218365A1

公开(公告)日：2021-07-15

申请号：US16837660

申请日：2020-04-01

Applicant: Microchip Technology Incorporated

Inventor： Yaojian Leng

IPC: H03B5/12 ,  H01F27/28 ,  H01L27/01 ,  H01L49/02 ,  H01L21/70

Abstract: A system-on-chip may include an inductor-capacitor oscillator monolithically integrated into the system-on-chip The inductor-capacitor oscillator may be configured to improve frequency stability and reduce noise when compared to a resistor-capacitor oscillator. Methods of making integrated oscillators may involve forming an inductor at least partially while forming a BEOL structure on a substrate. A capacitor supported on and/or embedded within the semiconductor material of the substrate may be formed before or while forming the BEOL structure. The inductor may be connected to the capacitor in parallel at least partially utilizing the BEOL structure to form an integrated inductor-capacitor oscillator.

公开(公告)号：US20200225169A1

公开(公告)日：2020-07-16

申请号：US16683987

申请日：2019-11-14

Applicant: Microchip Technology Incorporated

Inventor： Yaojian Leng

IPC: G01N21/95 ,  H01L23/532 ,  H01L23/528 ,  H01L23/522 ,  H01L31/103 ,  H01L31/02 ,  H01L21/66 ,  G01N21/47 ,  G01N21/88

Abstract: Systems and methods for monitoring copper corrosion in an integrated circuit (IC) device are disclosed. A corrosion-sensitive structure formed in the IC device may include a p-type active region adjacent an n-type active region to define a p-n junction space charge region. A copper region formed over the silicon may be connected to both the p-region and n-region by respective contacts, to thereby define a short circuit. Light incident on the p-n junction space charge region, e.g., during a CMP process, creates a current flow through the metal region via the short circuit, which drives chemical reactions that cause corrosion in the copper region. Due to the short circuit configuration, the copper region is highly sensitive to corrosion. The corrosion-sensitive structure may be arranged with less corrosion-sensitive copper structures in the IC device, with the corrosion-sensitive structure used as a proxy to monitor for copper corrosion in the IC device.

公开(公告)号：US12130241B2

公开(公告)日：2024-10-29

申请号：US18093032

申请日：2023-01-04

Applicant: Microchip Technology Incorporated

Inventor： Yaojian Leng

IPC: G01N21/95 ,  G01N17/02 ,  G01N21/47 ,  G01N21/88 ,  H01L21/66 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L31/02 ,  H01L31/103

CPC classification number: G01N21/9501 ,  G01N17/02 ,  G01N21/47 ,  G01N21/8851 ,  H01L22/14 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53238 ,  H01L31/02005 ,  H01L31/103 ,  G01N2021/4735 ,  G01N2201/06113

Abstract: Systems and methods for monitoring copper corrosion in an integrated circuit (IC) device are disclosed. A corrosion-sensitive structure formed in the IC device may include a p-type active region adjacent an n-type active region to define a p-n junction space charge region. A copper region formed over the silicon may be connected to both the p-region and n-region by respective contacts, to thereby define a short circuit. Light incident on the p-n junction space charge region, e.g., during a CMP process, creates a current flow through the metal region via the short circuit, which drives chemical reactions that cause corrosion in the copper region. Due to the short circuit configuration, the copper region is highly sensitive to corrosion. The corrosion-sensitive structure may be arranged with less corrosion-sensitive copper structures in the IC device, with the corrosion-sensitive structure used as a proxy to monitor for copper corrosion in the IC device.

公开(公告)号：US20240006472A1

公开(公告)日：2024-01-04

申请号：US17881064

申请日：2022-08-04

Applicant: Microchip Technology Incorporated

Inventor： Yaojian Leng

IPC: H01L49/02

CPC classification number: H01L28/91

Abstract: A multi-capacitor module includes a stacked metal-insulator-metal (MIM) structure including a cup-shaped first electrode, a cup-shaped first insulator formed over the cup-shaped first electrode, a cup-shaped second electrode formed over the cup-shaped first insulator, a cup-shaped second insulator formed over the cup-shaped second electrode, a third electrode formed over the cup-shaped second insulator. The stacked MIM structure also includes a first sidewall spacer located between the cup-shaped first electrode and the cup-shaped second electrode, and a second sidewall spacer located between the cup-shaped second electrode and the third electrode. The cup-shaped first electrode, the cup-shaped second electrode, and the cup-shaped first insulator define a first capacitor, and the cup-shaped second electrode, the third electrode, and the cup-shaped second insulator define a second capacitor.

公开(公告)号：US11824080B2

公开(公告)日：2023-11-21

申请号：US17233342

申请日：2021-04-16

Applicant: Microchip Technology Incorporated

Inventor： Yaojian Leng

IPC: H01L23/532 ,  H01C17/075 ,  H01L49/02 ,  H01C7/00 ,  H01L23/00

CPC classification number: H01L28/24 ,  H01C7/006 ,  H01C17/075 ,  H01L23/53238 ,  H01L24/03 ,  H01L24/05

Abstract: A thin film resistor (TFR) module may be formed in copper interconnect in an integrated circuit device. A pair of displacement-plated TFR heads may be formed by forming a pair of copper TFR head elements (e.g., damascene trench elements) spaced apart from each other in a dielectric region, and displacement plating a barrier region on each TFR head element to form a displacement-plated TFR head. A TFR element may be formed on the pair of displacement-plated TFR heads to define a conductive path between the pair of TFR head elements through the TFR element and through the displacement-plated barrier region on each metal TFR head. Conductive contacts may be formed connected to the pair of displacement-plated TFR heads. The displacement-plated barrier regions may protect the copper TFR heads from copper corrosion and/or diffusion, and may comprise CoWP, CoWB, Pd, CoP, Ni, Co, Ni—Co alloy, or other suitable material.