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公开(公告)号：US20220391330A1
公开(公告)日：2022-12-08
申请号：US17888392
申请日：2022-08-15
Applicant: Micron Technology, Inc.
Inventor： Samuel E. Bradshaw , Shivam Swami , Sean Stephen Eilert , Justin M. Eno , Ameen D. Akel
IPC: G06F13/10 , G06F3/06 , G06F13/12 , G06F12/0802
Abstract: A memory chip having a first set of pins configured to allow the memory chip to be coupled to a first microchip or device via first wiring. The memory chip also having a second set of pins configured to allow the memory chip to be coupled to a second microchip or device via second wiring that is separate from the first wiring. The memory chip also having a data mover configured to facilitate access to the second microchip or device, via the second set of pins, to read data from the second microchip or device and write data to the second microchip or device. Also, a system having the memory chip, the first microchip or device, and the second microchip or device.
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公开(公告)号：US11494311B2
公开(公告)日：2022-11-08
申请号：US16573527
申请日：2019-09-17
Applicant: Micron Technology, Inc.
Inventor： Samuel E. Bradshaw , Justin M. Eno , Sean S. Eilert , Shivasankar Gunasekaran , Hongyu Wang , Shivam Swami
IPC: G06F12/1009 , G06F12/1027
Abstract: A computer system includes physical memory devices of different types that store randomly-accessible data in memory of the computer system. In one approach, access to memory in an address space is maintained by an operating system of the computer system. A virtual page is associated with a first memory type. A page table entry is generated to map a virtual address of the virtual page to a physical address in a first memory device of the first memory type. The page table entry is used by a memory management unit to store the virtual page at the physical address.
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公开(公告)号：US20220107835A1
公开(公告)日：2022-04-07
申请号：US17553051
申请日：2021-12-16
Applicant: Micron Technology, Inc.
Inventor： Justin M. Eno
IPC: G06F9/48
Abstract: Systems, apparatuses, and methods to implement time to live for memory access by processors. For example, a processor has a register configured to store a parameter specifying a time duration indicative of the desired time to live. A memory system has multiple components with different latencies for memory access. When the memory controller of the processor sends a command to the memory system to load an item from a memory address, the memory system can fail to provide, to the processor within the time duration, the item from the memory address currently being hosted in a first component. In response, the memory controller can send a signal to abort the command; and the memory system can select a second component having a memory access latency shorter than the first component, and change the hosting of the memory address from in the first component to in the second component.
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公开(公告)号：US11163490B2
公开(公告)日：2021-11-02
申请号：US16573785
申请日：2019-09-17
Applicant: Micron Technology, Inc.
Inventor： Kenneth Marion Curewitz , Shivam Swami , Samuel E. Bradshaw , Justin M. Eno , Ameen D. Akel , Sean S. Eilert
Abstract: A memory chip having a predefined memory region configured to store program data transmitted from a microchip. The memory chip also having a programmable engine configured to facilitate access to a second memory chip to read data from the second memory chip and write data to the second memory chip according to stored program data in the predefined memory region. The predefined memory region can include a portion configured as a command queue for the programmable engine, and the programmable engine can be configured to facilitate access to the second memory chip according to the command queue.
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公开(公告)号：US20210271573A1
公开(公告)日：2021-09-02
申请号：US17323816
申请日：2021-05-18
Applicant: Micron Technology, Inc.
Inventor： Samuel E. Bradshaw , Justin M. Eno
IPC: G06F11/14 , G06F3/06 , G06F1/3225 , G06F11/10
Abstract: The present disclosure includes apparatuses and methods for performing data restore operations in memory. An embodiment includes a memory, and a controller configured to perform a data restore operation on data stored in the memory using a first table and a second table stored in the controller, wherein the first table includes a current mapping of the data stored in the memory that is based on a previous assessment of previous error rates associated with the data stored in the memory, and the second table includes a new mapping of the data stored in the memory that is based on a current assessment of current error rates associated with the data stored in the memory.
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Patent Agency Ranking
公开(公告)号：US20210081325A1
公开(公告)日：2021-03-18
申请号：US16573535
申请日：2019-09-17
Applicant: Micron Technology, Inc.
Inventor： Samuel E. Bradshaw , Shivasankar Gunasekaran , Hongyu Wang , Justin M. Eno
IPC: G06F12/1009 , G06F12/1027 , G06F3/06 , G06F9/50
Abstract: A computer system includes physical memory devices of different types that store randomly-accessible data in a main memory of the computer system. In one approach, an operating system allocates memory from a namespace for use by an application. The namespace is a logical reference to physical memory devices in which physical addresses are defined. The namespace is bound to a memory type. In response to binding the namespace to the memory type, the operating system adjusts a page table to map a logical memory address in the namespace to a memory device of the memory type.
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公开(公告)号：US10318381B2
公开(公告)日：2019-06-11
申请号：US15472957
申请日：2017-03-29
Applicant: Micron Technology, Inc.
Inventor： Justin M. Eno , Samuel E. Bradshaw
Abstract: A memory device can include three-dimensional memory entities each including a plurality of two-dimensional memory entities. A controller can read data from the memory at a first resolution and collect error rate information from the memory at a second resolution including a portion of a two-dimensional memory entity. The controller can determine a quantity of two-dimensional memory entities that have a greater error rate than a remainder of the two-dimensional memory entities based on the error rate information. The controller can determine a quantity of portions of three-dimensional memory entities that have a greater error rate than a remainder of the portions of three-dimensional memory entities based on the error rate information excluding error rate information for portions of the two-dimensional memory entities associated with the quantity of two-dimensional memory entities. The controller can cull the quantity of the two-dimensional memory entities and the quantity of the three-dimensional memory entities.
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公开(公告)号：US20230236747A1
公开(公告)日：2023-07-27
申请号：US18190669
申请日：2023-03-27
Applicant: Micron Technology, Inc.
Inventor： Kenneth Marion Curewitz , Shivasankar Gunasekaran , Ameen D. Akel , Hongyu Wang , Justin M. Eno , Shivam Swami , Samuel E. Bradshaw
IPC: G06F3/06 , G06F12/1027
CPC classification number: G06F3/0631 , G06F3/0673 , G06F3/0607 , G06F12/1027
Abstract: A computer system stores metadata that is used to identify physical memory devices that store randomly-accessible data for memory of the computer system. In one approach, access to memory in an address space is maintained by an operating system of the computer system. Stored metadata associates a first address range of the address space with a first memory device, and a second address range of the address space with a second memory device. The operating system manages processes running on the computer system by accessing the stored metadata. This management includes allocating memory based on the stored metadata so that data for a first process is stored in the first memory device, and data for a second process is stored in the second memory device.
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公开(公告)号：US11599430B2
公开(公告)日：2023-03-07
申请号：US17323816
申请日：2021-05-18
Applicant: Micron Technology, Inc.
Inventor： Samuel E. Bradshaw , Justin M. Eno
Abstract: The present disclosure includes apparatuses and methods for performing data restore operations in memory. An embodiment includes a memory, and a controller configured to perform a data restore operation on data stored in the memory using a first table and a second table stored in the controller, wherein the first table includes a current mapping of the data stored in the memory that is based on a previous assessment of previous error rates associated with the data stored in the memory, and the second table includes a new mapping of the data stored in the memory that is based on a current assessment of current error rates associated with the data stored in the memory.
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公开(公告)号：US11526450B2
公开(公告)日：2022-12-13
申请号：US17192744
申请日：2021-03-04
Applicant: Micron Technology, Inc.
Inventor： Samuel E. Bradshaw , Shivasankar Gunasekaran , Hongyu Wang , Justin M. Eno
IPC: G06F12/1009 , G06F12/1027 , G06F3/06 , G06F9/50
Abstract: A computer system includes physical memory devices of different types that store randomly-accessible data in a main memory of the computer system. In one approach, an operating system allocates memory from a namespace for use by an application. The namespace is a logical reference to physical memory devices in which physical addresses are defined. The namespace is bound to a memory type. In response to binding the namespace to the memory type, the operating system adjusts a page table to map a logical memory address in the namespace to a memory device of the memory type.
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