公开(公告)号：US12035543B2

公开(公告)日：2024-07-09

申请号：US17064099

申请日：2020-10-06

Applicant: Micron Technology, Inc.

Inventor： Hernan A. Castro ,  Stephen H. Tang ,  Stephen W. Russell

IPC: H10B63/00 ,  H10B53/20 ,  H10N70/20

CPC classification number: H10B63/845 ,  H10B53/20 ,  H10B63/20 ,  H10B63/22 ,  H10B63/24 ,  H10B63/80 ,  H10B63/84 ,  H10N70/235 ,  H10N70/245

Abstract: Methods and apparatuses for a cross-point memory array and related fabrication techniques are described. The fabrication techniques described herein may facilitate concurrently building two or more decks of memory cells disposed in a cross-point architecture. Each deck of memory cells may include a plurality of first access lines (e.g., word lines), a plurality of second access lines (e.g., bit lines), and a memory component at each topological intersection of a first access line and a second access line. The fabrication technique may use a pattern of vias formed at a top layer of a composite stack, which may facilitate building a 3D memory array within the composite stack while using a reduced number of processing steps. The fabrication techniques may also be suitable for forming a socket region where the 3D memory array may be coupled with other components of a memory device.

公开(公告)号：US11501828B2

公开(公告)日：2022-11-15

申请号：US17107639

申请日：2020-11-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Stephen H. Tang

IPC: G11C11/00 ,  G11C13/00 ,  G11C8/08 ,  G11C8/10

Abstract: Apparatuses, memories, and methods for decoding memory addresses for selecting access lines in a memory are disclosed. An example apparatus includes an address decoder circuit coupled to first and second select lines, a polarity line, and an access line. The first select line is configured to provide a first voltage, the second select line is configured to provide a second voltage, and the polarity line is configured to provide a polarity signal. The address decoder circuit is configured to receive address information and further configured to couple the access line to the first select line responsive to the address information having a combination of logic levels and the polarity signal having a first logic level and further configured to couple the access line to the second select line responsive to the address information having the combination of logic levels and the polarity signal having a second logic level.

公开(公告)号：US20210167127A1

公开(公告)日：2021-06-03

申请号：US17174027

申请日：2021-02-11

Applicant: Micron Technology, Inc.

Inventor： Hernan A. Castro ,  Stephen H. Tang ,  Stephen W. Russell

IPC: H01L27/24 ,  H01L27/11514

Abstract: Methods and apparatuses for a cross-point memory array and related fabrication techniques are described. The fabrication techniques described herein may facilitate concurrently building two or more decks of memory cells disposed in a cross-point architecture. Each deck of memory cells may include a plurality of first access lines (e.g., word lines), a plurality of second access lines (e.g., bit lines), and a memory component at each topological intersection of a first access line and a second access line. The fabrication technique may use a pattern of vias formed at a top layer of a composite stack, which may facilitate building a 3D memory array within the composite stack while using a reduced number of processing steps. The fabrication techniques may also be suitable for forming a socket region where the 3D memory array may be coupled with other components of a memory device.

公开(公告)号：US20210082503A1

公开(公告)日：2021-03-18

申请号：US17107639

申请日：2020-11-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Stephen H. Tang

IPC: G11C13/00 ,  G11C8/08

Abstract: Apparatuses, memories, and methods for decoding memory addresses for selecting access lines in a memory are disclosed. An example apparatus includes an address decoder circuit coupled to first and second select lines, a polarity line, and an access line. The first select line is configured to provide a first voltage, the second select line is configured to provide a second voltage, and the polarity line is configured to provide a polarity signal. The address decoder circuit is configured to receive address information and further configured to couple the access line to the first select line responsive to the address information having a combination of logic levels and the polarity signal having a first logic level and further configured to couple the access line to the second select line responsive to the address information having the combination of logic levels and the polarity signal having a second logic level.

公开(公告)号：US20210035612A1

公开(公告)日：2021-02-04

申请号：US17062024

申请日：2020-10-02

Applicant: Micron Technology, Inc.

Inventor： Hernan A. Castro ,  Stephen W. Russell ,  Stephen H. Tang

IPC: G11C5/06 ,  H01L27/105 ,  G11C8/10 ,  H01L23/50

Abstract: Methods and apparatuses for thin film transistors and related fabrication techniques are described. The thin film transistors may access two or more decks of memory cells disposed in a cross-point architecture. The fabrication techniques may use one or more patterns of vias formed at a top layer of a composite stack, which may facilitate building the thin film transistors within the composite stack while using a reduced number of processing steps. Different configurations of the thin film transistors may be built using the fabrication techniques by utilizing different groups of the vias. Further, circuits and components of a memory device (e.g., decoder circuitry, interconnects between aspects of one or more memory arrays) may be constructed using the thin film transistors as described herein along with related via-based fabrication techniques.

公开(公告)号：US20190327835A1

公开(公告)日：2019-10-24

申请号：US15961550

申请日：2018-04-24

Applicant: Micron Technology, Inc.

Inventor： Hernan A. Castro ,  Stephen W. Russell ,  Stephen H. Tang

IPC: H05K3/00 ,  H05K3/22 ,  H05K1/11

Abstract: Methods, systems, and devices for buried lines and related fabrication techniques are described. An electronic device (e.g., an integrated circuit) may include multiple buried lines at multiple layers of a stack. For example, a first layer of the stack may include multiple buried lines formed based on a pattern of vias formed at an upper layer of the stack. The pattern of vias may be formed in a wide variety of spatial configurations, and may allow for conductive material to be deposited at a buried target layer. In some cases, buried lines may be formed at multiple layers of the stack concurrently.