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公开(公告)号：US09954436B2
公开(公告)日：2018-04-24
申请号：US13876518
申请日：2011-09-29
申请人： Nadim Khlat
发明人： Nadim Khlat
CPC分类号： H02M3/07 , H02M2001/009 , Y10T307/406
摘要： The detailed description described embodiments of highly efficient power management systems configurable to simultaneously generate various output voltage levels for different components, sub-assemblies, and devices of electronic devices, sub-systems, and systems. In particular, the described embodiments include power management systems that substantially reduce or eliminate the need for inductors, large numbers of capacitors, and complex switching techniques to transform an available voltage level from a system power source, such as a battery, to more desirable power supply voltages. Some described embodiments include a charge pump that uses only two flying capacitors to simultaneously generate multiple supply outputs, where each of the multiple supply outputs may provide either the same or a different output voltage level. The described embodiments also include efficient power management systems that flexibly provide highly accurate voltage levels that are substantially insensitive to the voltage level provided by a system power source, such as a battery.
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公开(公告)号：US09112570B2
公开(公告)日：2015-08-18
申请号：US13020548
申请日：2011-02-03
申请人： Nadim Khlat , Marcus Granger-Jones
发明人： Nadim Khlat , Marcus Granger-Jones
CPC分类号： H04B1/1036
摘要： A tunable receiver system uses programmable notch filters to identify available channel pairs for transmitting and receiving data via a femtocell base station. In addition, one of the programmable notch filters may be used to suppress infiltration of the transmit path signal into the receiver path of the receiver device. The other programmable notch filter may be used to suppress a blocker signal identified by the receiver device.
摘要翻译： 可调谐接收机系统使用可编程陷波滤波器来识别用于经由毫微微小区基站发送和接收数据的可用信道对。 此外，可编程陷波滤波器之一可以用于抑制发射路径信号进入接收机设备的接收机路径的渗透。 另一个可编程陷波滤波器可用于抑制由接收机设备识别的阻塞信号。
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公开(公告)号：US09075673B2
公开(公告)日：2015-07-07
申请号：US13297470
申请日：2011-11-16
申请人： Nadim Khlat , Shanthi Prasad
发明人： Nadim Khlat , Shanthi Prasad
CPC分类号： G06F7/556 , G06F1/0307 , H03F1/0227 , H03M7/04
摘要： A digital log gain to digital linear gain multiplier is disclosed. The digital log gain to digital linear gain multiplier includes a log gain splitter adapted to split a log gain input into an integer log part and a remainder log part. A log scale-to-linear scale converter is adapted to output a linear gain value in response to the integer log part and the remainder log part. A gain multiply circuit is adapted to multiply a digital signal by the linear gain value to output a gain-enhanced digital signal.
摘要翻译： 公开了对数字线性增益乘数的数字对数增益。 对数字线性增益乘数的数字对数增益包括一个对数增益分配器，适用于将日志增益输入分解为整数对数部分和余数对数部分。 对数缩放比例转换器适于响应于整数对数部分和其余日志部分输出线性增益值。 增益乘法电路适于将数字信号乘以线性增益值以输出增益增强数字信号。
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公开(公告)号：US08942313B2
公开(公告)日：2015-01-27
申请号：US13367973
申请日：2012-02-07
CPC分类号： H03F1/0227 , H03F3/24 , H03F2200/411 , H03F2200/447 , H03F2200/465
摘要： An open loop envelope tracking system calibration technique and circuitry are proposed. A radio frequency power amplifier receives a modulated signal. An envelope tracker power converter generates a modulated power amplifier supply voltage for the radio frequency power amplifier based on a control signal derived from the modulated signal. A first output power and a second output power of the radio frequency power amplifier are measured when the control signal is respectively delayed by a first delay period and a second delay period. A sensitivity of the output power of the radio frequency power amplifier is near a maximum near the first delay period and the second delay period. The first delay period and/or the second delay period are adjusted until the first output power substantially equals the second output power. The first delay period and the second delay period are used to obtain a calibrated fine tuning delay offset.
摘要翻译： 提出了开环包络跟踪系统校准技术和电路。 射频功率放大器接收调制信号。 信封跟踪器功率转换器基于从调制信号导出的控制信号，为射频功率放大器生成调制功率放大器电源电压。 当控制信号分别延迟第一延迟周期和第二延迟周期时，测量射频功率放大器的第一输出功率和第二输出功率。 射频功率放大器的输出功率的灵敏度在第一延迟周期和第二延迟周期附近接近最大值。 第一延迟周期和/或第二延迟周期被调整直到第一输出功率基本上等于第二输出功率。 第一延迟周期和第二延迟周期用于获得经校准的微调延迟偏移。
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公开(公告)号：US08682260B1
公开(公告)日：2014-03-25
申请号：US12607634
申请日：2009-10-28
CPC分类号： H04B1/0475 , H04B1/0067
摘要： The present disclosure relates to a multi-band RF power amplifier (PA) module, which is used to receive, filter, and amplify a first RF input signal to provide a first RF output signal using a first tunable bandpass and notch filter. The multi-band RF PA module may include a supporting substrate having at least a first inductive element that provides a first portion of the first tunable bandpass and notch filter. Further, the multi-band RF PA module may include at least a first semiconductor die, which is attached to the supporting substrate and provides a second portion of the first tunable bandpass and notch filter. A transceiver module may provide the first RF input signal.
摘要翻译： 本公开涉及一种多频带RF功率放大器（PA）模块，其用于接收，滤波和放大第一RF输入信号，以使用第一可调谐带通和陷波滤波器提供第一RF输出信号。 多频带RF PA模块可以包括具有至少第一感应元件的支撑衬底，其提供第一可调谐带通和陷波滤波器的第一部分。 此外，多频带RF PA模块可以包括至少第一半导体管芯，其连接到支撑衬底并提供第一可调谐带通和陷波滤波器的第二部分。 收发器模块可以提供第一RF输入信号。
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36.发明授权Split-band power amplifiers and duplexers for LTE-advanced front end for improved IMD 有权用于LTE高级前端的分频功率放大器和双工器，用于改进IMD公开(公告)号：US08644198B2
公开(公告)日：2014-02-04
申请号：US13045621
申请日：2011-03-11
IPC分类号： H04B7/00
CPC分类号： H03F3/24 , H03F3/189 , H03F3/211 , H03F3/68 , H03F2200/222 , H03F2200/249 , H03F2200/318 , H03F2200/387 , H03F2200/411 , H03F2200/451 , H03F2200/534 , H03F2200/537 , H03F2200/541 , H03F2200/81
摘要： A front end radio architecture (FERA) is disclosed that includes a transmitter block coupled to a power amplifier (PA) via first and second input terminals. A first split-band duplexer is coupled to a first output terminal of the PA and a second split-band duplexer is coupled to a second output terminal of the PA. The PA includes a first amplifier cell and a second amplifier cell that when coupled to the first and second split-band duplexers makes up first and second transmitter chains. Only one of the first and the second transmitter chains is active when a first carrier and a second carrier have a frequency offset that is less than an associated half duplex frequency within a same split-band duplex band, thus preventing third order inter-modulation (IMD) products from falling within an associated receive channel. Otherwise, the first and the second transmitter chains are both active.
摘要翻译： 公开了一种前端无线电架构（FERA），其包括经由第一和第二输入端子耦合到功率放大器（PA）的发射机模块。 第一分波分双工器耦合到PA的第一输出端，而第二分波分双工器耦合到PA的第二输出端。 PA包括第一放大器单元和第二放大器单元，当耦合到第一和第二分离带双工器组成第一和第二发送器链时。 当第一载波和第二载波具有小于相同分离带双工频带内的相关联的半双工频率的频率偏移时，第一和第二发射机链中只有一个有效，从而防止三阶互调（ IMD）产品落入相关接收渠道内。 否则，第一和第二发射机链都是活动的。
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37.发明授权Extracting clock information from a serial communications bus for use in RF communications circuitry 有权从串行通信总线提取时钟信息，用于RF通信电路公开(公告)号：US08521101B1
公开(公告)日：2013-08-27
申请号：US12884933
申请日：2010-09-17
IPC分类号： H04B1/38
CPC分类号： H04L7/04 , G06F13/385 , H04J3/0685
摘要： The present disclosure relates to RF front-end (RFFE) circuitry that includes multiple RFFE circuits, each of which may be provided by a separate integrated circuit (IC), front-end module, or both. As such, the RFFE circuits may be connected to one another using an RFFE serial communications bus. Further, one or more of the RFFE circuits may need an accurate clock source for analog-to-digital conversion (ADC), digital-to-analog conversion (DAC), calibration, sensor measurements, or the like. Instead of including an integral clock source circuit or receiving a separate external clock signal, an RFFE circuit may extract clock information from the RFFE serial communications bus to provide one or more clock signal. The clock information may be associated with one or more serial communications command via the RFFE serial communications bus, may be associated with alternate functionality of the RFFE serial communications bus, or both.
摘要翻译： 本公开涉及包括多个RFFE电路的RF前端（RFFE）电路，每个RFFE电路可以由单独的集成电路（IC），前端模块或两者提供。 因此，RFFE电路可以使用RFFE串行通信总线彼此连接。 此外，一个或多个RFFE电路可能需要用于模数转换（ADC），数模转换（DAC），校准，传感器测量等的精确时钟源。 RFFE电路不是包括集成时钟源电路或者接收单独的外部时钟信号，而是可以从RFFE串行通信总线提取时钟信息以提供一个或多个时钟信号。 时钟信息可以经由RFFE串行通信总线与一个或多个串行通信命令相关联，可以与RFFE串行通信总线或两者的备用功能相关联。
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38.发明授权公开(公告)号：US08442076B1
公开(公告)日：2013-05-14
申请号：US12894404
申请日：2010-09-30
申请人： Nadim Khlat
发明人： Nadim Khlat
CPC分类号： H04J3/0605 , H04J3/0632
摘要： A timing control system includes a counter that is initiated by a time accurate strobe (TAS) signal. A counter value is recorded when a message arrives in a buffer. A baseband integrated circuit (BBIC) calculates an integer number of counter periods and a fraction of a counter period corresponding to a timing correction value received from a base station. The BBIC issues a TAS signal during a counter period that occurs at the integer number of counter periods. At an expiration of the fraction of an ensuing counter period, the first one of a plurality of frame time slots is sent from the buffer to an antenna via a radio frequency integrated circuit (RFIC). The BBIC calculates, then stores in a memory, timing adjust values for the plurality of frame time slots so that each frame time slot can be time adjusted during message transmissions without an issuance of an additional TAS signal.
摘要翻译： 定时控制系统包括由时间精确选通（TAS）信号启动的计数器。 当消息到达缓冲区时记录计数器值。 基带集成电路（BBIC）计算整数个计数器周期和与从基站接收到的定时校正值对应的计数器周期的一部分。 BBIC在整数个计数周期发生的计数器周期内发出TAS信号。 在随后的计数器周期的一小部分到期时，多个帧时隙中的第一个时隙通过射频集成电路（RFIC）从缓冲器发送到天线。 BBIC计算然后存储在存储器中，定时调整多个帧时隙的值，使得每个帧时隙可以在消息传输期间被时间调整，而不发出额外的TAS信号。
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公开(公告)号：US20130051284A1
公开(公告)日：2013-02-28
申请号：US13569219
申请日：2012-08-08
申请人： Nadim Khlat
发明人： Nadim Khlat
IPC分类号： H04W72/04
摘要： A carrier aggregation radio system is provided. The carrier aggregation radio system includes a transceiver having a main receiver, a diversity receiver and a carrier aggregation receiver. The carrier aggregation radio system further includes a control system adapted to command a radio front end to route diversity signals from a diversity antenna to the main and diversity receivers in a first mode and to command the radio front end to route carrier aggregation signals from the diversity antenna to the carrier aggregation receiver in a second mode. The control system may also command a third mode in which diversity signals are routed to the main and diversity receivers while carrier aggregation signals are routed to the carrier aggregation receiver.
摘要翻译： 提供载波聚合无线电系统。 载波聚合无线电系统包括具有主接收机，分集接收机和载波聚合接收机的收发机。 载波聚合无线电系统还包括控制系统，其适于命令无线电前端以分集天线将分集信号以第一模式路由到主分集接收机，并命令无线电前端从分集路由载波聚合信号 在第二模式中天线到载波聚合接收机。 控制系统还可以命令第三模式，其中分集信号被路由到主和分集接收机，而载波聚合信号被路由到载波聚合接收机。
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公开(公告)号：US20130043932A1
公开(公告)日：2013-02-21
申请号：US13222484
申请日：2011-08-31
申请人： Nadim Khlat , Joseph Hubert Colles
发明人： Nadim Khlat , Joseph Hubert Colles
IPC分类号： G05F3/02
CPC分类号： H02M3/07 , H02M2001/009
摘要： Disclosed is a charge pump system having a charge pump with a switch control input, a voltage output terminal, a high voltage terminal coupled to a high voltage node and a low voltage terminal coupled to a low voltage node. Also included is a first buck/boost switch having a first terminal coupled to the voltage output terminal, a second terminal coupled to a first output node, and a first control terminal for receiving a first control signal. A second buck/boost switch includes a first terminal coupled to the voltage output terminal, a second terminal coupled to a second output node, and a control terminal for receiving a second control signal. Further included is a switch controller that is adapted to generate the first control signal and the second control signal such that voltage pulses output from the first output node and the second output node, respectively, are asymmetrical and coincidental.
摘要翻译： 公开了一种具有电荷泵的电荷泵系统，其具有开关控制输入端，电压输出端子，耦合到高电压节点的高电压端子和耦合到低压节点的低电压端子。 还包括第一降压/升压开关，其具有耦合到电压输出端的第一端子，耦合到第一输出节点的第二端子和用于接收第一控制信号的第一控制端子。 第二降压/升压开关包括耦合到电压输出端的第一端子，耦合到第二输出节点的第二端子和用于接收第二控制信号的控制端子。 还包括开关控制器，其适于产生第一控制信号和第二控制信号，使得分别从第一输出节点和第二输出节点输出的电压脉冲是不对称和巧合的。
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