公开(公告)号：US12003778B2

公开(公告)日：2024-06-04

申请号：US17830577

申请日：2022-06-02

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Virginie Drugeon ,  Takahiro Nishi ,  Kiyofumi Abe ,  Tadamasa Toma ,  Yusuke Kato

IPC: H04N19/70 ,  H04N19/172 ,  H04N19/174

CPC classification number: H04N19/70 ,  H04N19/172 ,  H04N19/174

Abstract: An encoder includes circuitry and memory coupled to the circuitry. The circuitry: assigns a picture level slice index and a subpicture level slice index to each of the slices, the picture level slice index being assigned at a picture level, the subpicture level slice index being assigned at a subpicture level; for each of the slices, encodes the subpicture level slice index of the slice into a slice header of the slice; and encodes each of the slices into a bitstream. The picture level slice index assigned to a current slice to be processed that is included in a current subpicture to be processed is calculated by adding (i) the subpicture level slice index of the current slice and (ii) a total number of slices included in one or more subpictures that have been encoded prior to the current subpicture out of the subpictures.

公开(公告)号：US11849147B2

公开(公告)日：2023-12-19

申请号：US17725084

申请日：2022-04-20

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Jing Ya Li ,  Che Wei Kuo ,  Chong Soon Lim ,  Chu Tong Wang ,  Han Boon Teo ,  Hai Wei Sun ,  Kiyofumi Abe ,  Takahiro Nishi ,  Tadamasa Toma ,  Yusuke Kato

IPC: H04N19/66 ,  H04N19/122 ,  H04N19/176 ,  H04N19/103 ,  H04N19/96

CPC classification number: H04N19/66 ,  H04N19/122 ,  H04N19/176 ,  H04N19/103 ,  H04N19/96

Abstract: An encoder determines, based on a width and a height of a block, whether or not to disable a prediction mode in which the block is split along a partitioning line defined by a distance and an angle and then prediction is performed; and encodes the block with the prediction mode disabled or not disabled according to a result of the determination on whether or not to disable the prediction mode. Here, the distance is the shortest distance between the center of the block and the partitioning line, and the angle is an angle representing a direction from the center of the block toward the partitioning line in the shortest distance. The encoder determines to disable the prediction mode when (i) a width-to-height ratio is at least 8 or (ii) a height-to-width ratio is at least 8.

公开(公告)号：US11825126B2

公开(公告)日：2023-11-21

申请号：US17507571

申请日：2021-10-21

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Jing Ya Li ,  Han Boon Teo ,  Chong Soon Lim ,  Hai Wei Sun ,  Che-Wei Kuo ,  Chu Tong Wang ,  Tadamasa Toma ,  Takahiro Nishi ,  Kiyofumi Abe ,  Yusuke Kato

IPC: H04N19/82 ,  H04N19/107 ,  H04N19/176 ,  H04N19/186

CPC classification number: H04N19/82 ,  H04N19/107 ,  H04N19/176 ,  H04N19/186

Abstract: A decoder includes memory and a processor coupled to the memory and configured to: generate a first coefficient value by applying a CCALF (cross component adaptive loop filtering) process to a first reconstructed image sample of a luma component; clip the first coefficient value such that the clipped first coefficient value is within a first range from −27 to 27−1; generate a second coefficient value by applying an ALF (adaptive loop filtering) process to a second reconstructed image sample of a chroma component; clip the second coefficient value such that the clipped second coefficient value is within a second range different from the first range; generate a third coefficient value by adding the clipped first coefficient value to the clipped second coefficient value; and generate a third reconstructed image sample of the chroma component using the third coefficient value.

公开(公告)号：US11812045B2

公开(公告)日：2023-11-07

申请号：US17833986

申请日：2022-06-07

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Takahiro Nishi ,  Tadamasa Toma ,  Kiyofumi Abe ,  Yusuke Kato

IPC: H04N19/44 ,  H04N19/119 ,  H04N19/176 ,  H04N19/70

CPC classification number: H04N19/44 ,  H04N19/119 ,  H04N19/176 ,  H04N19/70

Abstract: According to one aspect of the present disclosure, a decoder includes memory and a processor coupled to the memory. The processor is configured to split a current picture into tiles, generate a slice having a rectangular shape and located at a lower-right corner of the current picture, the slice including at least a part of a tile among the tiles, generate first information on a region of the slice with header information, the header information not including information identical to the first information, and decode the slice with the first information.

公开(公告)号：US11722699B2

公开(公告)日：2023-08-08

申请号：US17726248

申请日：2022-04-21

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Jing Ya Li ,  Che Wei Kuo ,  Chong Soon Lim ,  Chu Tong Wang ,  Han Boon Teo ,  Hai Wei Sun ,  Kiyofumi Abe ,  Takahiro Nishi ,  Tadamasa Toma ,  Yusuke Kato

IPC: H04N19/66 ,  H04N19/122 ,  H04N19/176 ,  H04N19/103 ,  H04N19/96

CPC classification number: H04N19/66 ,  H04N19/122 ,  H04N19/176 ,  H04N19/103 ,  H04N19/96

Abstract: An encoder determines, based on a width and a height of a block, whether or not to disable a prediction mode in which the block is split along a partitioning line defined by a distance and an angle and then prediction is performed; and encodes the block with the prediction mode disabled or not disabled according to a result of the determination on whether or not to disable the prediction mode. Here, the distance is the shortest distance between the center of the block and the partitioning line, and the angle is an angle representing a direction from the center of the block toward the partitioning line in the shortest distance. The encoder determines to disable the prediction mode when (i) a width-to-height ratio is at least 8 or (ii) a height-to-width ratio is at least 8.

公开(公告)号：US11689714B2

公开(公告)日：2023-06-27

申请号：US17368123

申请日：2021-07-06

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Tadamasa Toma ,  Takahiro Nishi ,  Kiyofumi Abe ,  Yusuke Kato

IPC: H04N19/105 ,  H04N19/176 ,  H04N19/182

CPC classification number: H04N19/105 ,  H04N19/176 ,  H04N19/182

Abstract: An encoder includes circuitry and memory connected to the circuitry. The circuitry, in operation: derives, as a first parameter, a total sum of absolute values of sums of horizontal gradient values respectively for pairs of relative pixel positions; derives, as a second parameter, a total sum of absolute values of sums of vertical gradient values respectively for the pairs of relative pixel positions; derives, as a third parameter, a total sum of horizontal-related pixel difference values respectively for the pairs of relative pixel positions; derives, as a fourth parameter, a total sum of vertical-related pixel difference values respectively for the pairs of relative pixel positions; derives, as a fifth parameter, a total sum of vertical-related sums of horizontal gradient values respectively for the pairs of relative pixel positions; and generates a prediction image to be used to encode the current block using the first, second, third, fourth, and fifth parameters.

公开(公告)号：US11677947B2

公开(公告)日：2023-06-13

申请号：US17377107

申请日：2021-07-15

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Tadamasa Toma ,  Takahiro Nishi ,  Kiyofumi Abe ,  Yusuke Kato

IPC: H04N19/124 ,  H04N19/136 ,  H04N19/157 ,  H04N19/176 ,  H04N19/61

CPC classification number: H04N19/124 ,  H04N19/136 ,  H04N19/157 ,  H04N19/176 ,  H04N19/61

Abstract: An encoder includes circuitry and memory coupled to the circuitry. In operation, the circuitry: performs quantization on a plurality of transform coefficients of a current block to be encoded, using a quantization matrix when orthogonal transform is performed on the current block and secondary transform is not performed on the current block; and performs quantization on the plurality of transform coefficients of the current block without using the quantization matrix when orthogonal transform is not performed on the current block and when both orthogonal transform and secondary transform are performed on the current block.

公开(公告)号：US11553195B2

公开(公告)日：2023-01-10

申请号：US17388426

申请日：2021-07-29

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Virginie Drugeon ,  Tadamasa Toma ,  Takahiro Nishi ,  Kiyofumi Abe ,  Yusuke Kato

IPC: H04N19/31

Abstract: An encoder includes circuitry, and memory coupled to the circuitry. The circuitry, in operation, for each of a plurality of sub-bitstreams having mutually different frame rates, encodes identification information into a header of a bitstream including the plurality of sub-bitstreams, the identification information indicating a temporal ID that is an identifier of a temporal layer related to a temporal scalability and corresponds to the sub-bitstream, and encodes level information indicating a conformance level of the sub-bitstream.

公开(公告)号：US11425424B2

公开(公告)日：2022-08-23

申请号：US16875553

申请日：2020-05-15

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Chong Soon Lim ,  Hai Wei Sun ,  Han Boon Teo ,  Jing Ya Li ,  Che-Wei Kuo ,  Tadamasa Toma ,  Takahiro Nishi ,  Kiyofumi Abe ,  Yusuke Kato

IPC: H04N19/82 ,  H04N19/119 ,  H04N19/176 ,  H04N19/593

Abstract: An encoder includes circuitry and memory coupled to the circuitry. The circuitry determines whether to split a current luma virtual pipeline decoding unit (VPDU) into smaller blocks. When it is determined not to split the current luma VPDU into smaller blocks, the circuitry predicts a block of chroma samples without using luma samples. When it is determined to split the luma VPDU into smaller blocks, the circuitry predicts the block of chroma samples using luma samples. The circuitry encodes the block using the predicted chroma samples.

公开(公告)号：US11388429B2

公开(公告)日：2022-07-12

申请号：US17241670

申请日：2021-04-27

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Takahiro Nishi ,  Tadamasa Toma ,  Kiyofumi Abe ,  Yusuke Kato

IPC: H04N19/44 ,  H04N19/119 ,  H04N19/176 ,  H04N19/70

Abstract: According to one aspect of the present disclosure, a decoder includes memory and a processor coupled to the memory. The processor is configured to split a current picture into tiles, generate a slice having a rectangular shape and located at a lower-right corner of the current picture, the slice including at least a part of a tile among the tiles, generate first information on a region of the slice with header information, the header information not including information identical to the first information, and decode the slice with the first information.