公开(公告)号：US08836040B2

公开(公告)日：2014-09-16

申请号：US13671114

申请日：2012-11-07

Applicant: QUALCOMM Incorporated

Inventor： Pratyush Kamal ,  Esin Terzioglu ,  Foua Vang ,  Prayag Bhanubhai Patel ,  Giridhar Nallapati ,  Animesh Datta

IPC: H01L21/70 ,  H01L21/8238 ,  H01L29/66 ,  H01L27/118 ,  H01L27/02 ,  H01L27/092

CPC classification number: H01L27/092 ,  H01L27/0207 ,  H01L27/11807 ,  H01L29/66545 ,  H01L2027/11831

Abstract: A semiconductor standard cell includes an N-type diffusion area and a P-type diffusion area, both extending across the cell and also outside of the cell. The cell also includes a conductive gate above each diffusion area to create a semiconductive device. A pair of dummy gates are also above the N-type diffusion area and the P-type diffusion area creating a pair of dummy devices. The pair of dummy gates are disposed at opposite edges of the cell. The cell further includes a first conductive line configured to couple the dummy devices to power for disabling the dummy devices.

Abstract translation: 半导体标准单元包括N型扩散区和P型扩散区，两者均延伸穿过电池并且还在电池外部。 电池还包括在每个扩散区域上方的导电栅极以产生半导体器件。 一对虚拟栅极也在N型扩散区域和P型扩散区域的上方，形成一对虚设装置。 一对虚拟门设置在电池的相对边缘。 电池还包括第一导线，其被配置为将虚设装置耦合到用于禁用虚设装置的电力。

公开(公告)号：US20140211893A1

公开(公告)日：2014-07-31

申请号：US13756491

申请日：2013-01-31

Applicant: QUALCOMM INCORPORATED

Inventor： Seid Hadi Rasouli ,  Animesh Datta ,  Saravanan Marimuthu ,  Ohsang Kwon

IPC: H04L7/00

CPC classification number: H04L7/0045 ,  H03K3/356156 ,  H04L7/0037

Abstract: Techniques for resolving a metastable state in a synchronizer are described herein. In one embodiment, a circuit for resolving a metastable state in a synchronizer comprises a signal delay circuit coupled to a node of the synchronizer, wherein the signal delay circuit is configured to delay a data signal at the node to produce a delayed data signal, and a transmission circuit coupled to the signal delay circuit, wherein the transmission circuit is configured to couple the delayed data signal to the node after a delay from a first edge of a clock signal.

Abstract translation: 本文描述了用于解决同步器中的亚稳态的技术。 在一个实施例中，用于分解同步器中的亚稳态的电路包括耦合到同步器的节点的信号延迟电路，其中信号延迟电路被配置为延迟节点处的数据信号以产生延迟的数据信号，以及 耦合到所述信号延迟电路的传输电路，其中所述传输电路被配置为在从时钟信号的第一边缘延迟之后将所述延迟的数据信号耦合到所述节点。