公开(公告)号：US20140211893A1

公开(公告)日：2014-07-31

申请号：US13756491

申请日：2013-01-31

Applicant: QUALCOMM INCORPORATED

Inventor： Seid Hadi Rasouli ,  Animesh Datta ,  Saravanan Marimuthu ,  Ohsang Kwon

IPC: H04L7/00

CPC classification number: H04L7/0045 ,  H03K3/356156 ,  H04L7/0037

Abstract: Techniques for resolving a metastable state in a synchronizer are described herein. In one embodiment, a circuit for resolving a metastable state in a synchronizer comprises a signal delay circuit coupled to a node of the synchronizer, wherein the signal delay circuit is configured to delay a data signal at the node to produce a delayed data signal, and a transmission circuit coupled to the signal delay circuit, wherein the transmission circuit is configured to couple the delayed data signal to the node after a delay from a first edge of a clock signal.

Abstract translation: 本文描述了用于解决同步器中的亚稳态的技术。 在一个实施例中，用于分解同步器中的亚稳态的电路包括耦合到同步器的节点的信号延迟电路，其中信号延迟电路被配置为延迟节点处的数据信号以产生延迟的数据信号，以及 耦合到所述信号延迟电路的传输电路，其中所述传输电路被配置为在从时钟信号的第一边缘延迟之后将所述延迟的数据信号耦合到所述节点。

公开(公告)号：US09053773B2

公开(公告)日：2015-06-09

申请号：US14025741

申请日：2013-09-12

Applicant: QUALCOMM Incorporated

Inventor： Saravanan Marimuthu ,  Sachin Bapat ,  Sakthivel Packirisamy

IPC: G11C7/10 ,  G11C7/00 ,  G11C7/08 ,  G11C8/16 ,  G11C8/00 ,  G11C8/12 ,  G11C8/18 ,  G11C29/00 ,  G11C5/06 ,  G11C7/22

CPC classification number: G11C8/16 ,  G11C5/06 ,  G11C7/00 ,  G11C7/10 ,  G11C7/1057 ,  G11C7/1075 ,  G11C7/222 ,  G11C8/18 ,  G11C29/818 ,  G11C2207/108 ,  Y10T29/49117

Abstract: An integrated circuit element is disclosed having a memory device; a P-type semiconductor region including a first semiconductor device from a first memory port circuit coupled to the memory device and configured to enable access to the memory device when the first semiconductor device is activated; an N-type semiconductor region including a second semiconductor device from a second memory port circuit coupled to the memory device and configured to enable access to the memory device when the second semiconductor device is activated; and a plurality of signal lines distributed over the P-type and N-type semiconductor regions including a first memory port selection line coupled to allow the first semiconductor device to be activated; a second memory port selection line coupled to allow the second semiconductor device to be activated; and a clock signal line placed between the first memory port selection line and the second memory port selection line.

Abstract translation: 公开了一种具有存储器件的集成电路元件; P型半导体区域，包括耦合到存储器件的第一存储器端口电路的第一半导体器件，并且被配置为当第一半导体器件被激活时能够访问存储器件; N型半导体区域，包括耦合到所述存储器件的第二存储器端口电路的第二半导体器件，并且被配置为当所述第二半导体器件被激活时能够访问所述存储器件; 以及分布在P型和N型半导体区域上的多条信号线，包括耦合以允许第一半导体器件被激活的第一存储器端口选择线; 耦合以允许第二半导体器件被激活的第二存储器端口选择线; 以及设置在第一存储器端口选择线和第二存储器端口选择线之间的时钟信号线。

公开(公告)号：US09020084B2

公开(公告)日：2015-04-28

申请号：US13756491

申请日：2013-01-31

Applicant: QUALCOMM Incorporated

Inventor： Seid Hadi Rasouli ,  Animesh Datta ,  Saravanan Marimuthu ,  Ohsang Kwon

IPC: H04L7/00 ,  H03K3/356

CPC classification number: H04L7/0045 ,  H03K3/356156 ,  H04L7/0037

Abstract: Techniques for resolving a metastable state in a synchronizer are described herein. In one embodiment, a circuit for resolving a metastable state in a synchronizer comprises a signal delay circuit coupled to a node of the synchronizer, wherein the signal delay circuit is configured to delay a data signal at the node to produce a delayed data signal, and a transmission circuit coupled to the signal delay circuit, wherein the transmission circuit is configured to couple the delayed data signal to the node after a delay from a first edge of a clock signal.

Abstract translation: 本文描述了用于解决同步器中的亚稳态的技术。 在一个实施例中，用于分解同步器中的亚稳态的电路包括耦合到同步器的节点的信号延迟电路，其中信号延迟电路被配置为延迟节点处的数据信号以产生延迟的数据信号，以及 耦合到所述信号延迟电路的传输电路，其中所述传输电路被配置为在从时钟信号的第一边缘延迟之后将所述延迟的数据信号耦合到所述节点。

公开(公告)号：US11823962B2

公开(公告)日：2023-11-21

申请号：US17180652

申请日：2021-02-19

Applicant: QUALCOMM Incorporated

Inventor： Saravanan Marimuthu ,  De Lu ,  Baldeo Sharan Sharma ,  Peeyush Kumar Parkar ,  Venkat Narayanan ,  Rui Li ,  Samy Shafik Tawfik Zaynoun ,  Min Chen ,  David Kidd ,  Amit Patil

IPC: H01L21/66 ,  G06F30/398

CPC classification number: H01L22/14 ,  G06F30/398 ,  H01L22/34

Abstract: Aspects of the disclosure are directed to sensing integrated circuit (IC) Back End Of Line (BEOL) process corners. In one aspect, an apparatus for sensing IC BEOL process corners includes a ring oscillator including a plurality of ring oscillator stages configured to generate an output waveform with a frequency state; and a shield net circuit including a plurality of shield net stages corresponding to the plurality of ring oscillator stages, the shield net circuit having a toggle input. And, a method includes generating an output waveform with a frequency state using a ring oscillator that includes a plurality of ring oscillator stages; modifying a plurality of ring oscillator stage time delays through a coupling between a plurality of shield net stages and the plurality of ring oscillator stages; and selecting the frequency state using a toggle input of a shield net circuit which includes the plurality of shield net stages.