公开(公告)号：US11803489B2

公开(公告)日：2023-10-31

申请号：US17849450

申请日：2022-06-24

Applicant: Rambus Inc.

Inventor： Pravin Kumar Venkatesan ,  Liji Gopalakrishnan ,  Kashinath Ullhas Prabhu ,  Makarand Ajit Shirasgaonkar

IPC: G06F13/16

CPC classification number: G06F13/1668 ,  Y02D10/00

Abstract: A single-ended receiver is coupled to an input-output (I/O) pin of a command and address (CA) bus. The receiver is configurable with dual-mode I/O support to operate the CA bus in a low-swing mode and a high-swing mode. The receiver is configurable to receive a first command on the I/O pin while in the high-swing mode, initiate calibration of the slave device to operate in the low-swing mode in response to the first command, switch the slave device to operate in the low-swing mode while the CA bus remains active, and to receive a second command on the I/O pin while in the low-swing mode.

公开(公告)号：US20230119579A1

公开(公告)日：2023-04-20

申请号：US18082446

申请日：2022-12-15

Applicant: Rambus Inc.

Inventor： Pravin Kumar Venkatesan ,  Liji Gopalakrishnan ,  Kashinath Ullhas Prabhu ,  Makarand Ajit Shirasgaonkar

IPC: G06F13/16

Abstract: A method of operation of a flash integrated circuit (IC) memory device is described. The flash IC memory device has an array of memory cells and an interface to receive control, address and data signals using an internal reference voltage. The method includes, at boot-up, initializing the internal reference voltage to a default voltage. At boot-up, the interface is operable to receive, using the internal reference voltage, signals having a first voltage swing at a first signaling frequency. The method includes receiving a first command that specifies calibration of the interface during a calibration mode. The calibration mode is used to calibrate the interface to operate at a second signaling frequency and receive signals having a second voltage swing. The second voltage swing is smaller than the first voltage swing and the second signaling frequency is higher than the first signaling frequency.

公开(公告)号：US20220291992A1

公开(公告)日：2022-09-15

申请号：US17721735

申请日：2022-04-15

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John E. Linstadt ,  Liji Gopalakrishnan

IPC: G06F11/10 ,  G06F3/06

Abstract: A memory system employs an addressing scheme to logically divide rows of memory cells into separate contiguous regions, one for data storage and another for error detection and correction (EDC) codes corresponding to that data. Data and corresponding EDC codes are stored in the same row of the same bank. Accessing data and corresponding EDC code in the same row of the same bank advantageously saves power and avoids bank conflicts. The addressing scheme partitions the memory without requiring the requesting processor to have an understanding of the memory partition.

公开(公告)号：US11372784B2

公开(公告)日：2022-06-28

申请号：US16709506

申请日：2019-12-10

Applicant: Rambus Inc.

Inventor： Pravin Kumar Venkatesan ,  Liji Gopalakrishnan ,  Kashinath Ullhas Prabhu ,  Makarand Ajit Shirasgaonkar

IPC: G06F13/16

Abstract: A single-ended receiver is coupled to an input-output (I/O) pin of a command and address (CA) bus. The receiver is configurable with dual-mode I/O support to operate the CA bus in a low-swing mode and a high-swing mode. The receiver is configurable to receive a first command on the I/O pin while in the high-swing mode, initiate calibration of the slave device to operate in the low-swing mode in response to the first command, switch the slave device to operate in the low-swing mode while the CA bus remains active, and to receive a second command on the I/O pin while in the low-swing mode.

公开(公告)号：US11049546B2

公开(公告)日：2021-06-29

申请号：US16865928

申请日：2020-05-04

Applicant: Rambus Inc.

Inventor： Ian Shaeffer ,  Lei Luo ,  Liji Gopalakrishnan

IPC: G11C11/4076 ,  G11C11/4096 ,  G11C7/10 ,  G11C7/20 ,  G11C7/22 ,  G11C11/4072 ,  G11C11/4074 ,  G06F1/3237 ,  G06F1/04 ,  G06F1/3234 ,  G06F1/08 ,  G11C11/408

Abstract: An integrated circuit includes a physical layer interface having a control timing domain and a data timing domain, and circuits that enable the control timing domain during a change in power conservation mode in response to a first event, and that enable the data timing domain in response to a second event. The control timing domain can include interface circuits coupled to a command and address path, and the data timing domain can include interface circuits coupled to a data path.

公开(公告)号：US20210011876A1

公开(公告)日：2021-01-14

申请号：US16942970

申请日：2020-07-30

Applicant: Rambus Inc.

Inventor： Liji Gopalakrishnan ,  Ian Shaeffer ,  Yi Lu

IPC: G06F13/40 ,  G11C7/10 ,  G11C11/4093 ,  G11C11/4094 ,  G11C5/04 ,  G06F13/16

Abstract: A memory device or module selects between alternative command ports. Memory systems with memory modules incorporating such memory devices support point-to-point connectivity and efficient interconnect usage for different numbers of modules. The memory devices and modules can be of programmable data widths. Devices on the same module can be configured select different command ports to facilitate memory threading. Modules can likewise be configured to select different command ports for the same purpose.

公开(公告)号：US10747703B2

公开(公告)日：2020-08-18

申请号：US16520137

申请日：2019-07-23

Applicant: Rambus Inc.

Inventor： Liji Gopalakrishnan ,  Ian Shaeffer ,  Yi Lu

IPC: G06F13/40 ,  G11C7/10 ,  G11C11/4093 ,  G11C11/4094 ,  G11C5/04 ,  G06F13/16 ,  G11C11/4096

Abstract: A memory device or module selects between alternative command ports. Memory systems with memory modules incorporating such memory devices support point-to-point connectivity and efficient interconnect usage for different numbers of modules. The memory devices and modules can be of programmable data widths. Devices on the same module can be configured select different command ports to facilitate memory threading. Modules can likewise be configured to select different command ports for the same purpose.

公开(公告)号：US20200218675A1

公开(公告)日：2020-07-09

申请号：US16709506

申请日：2019-12-10

Applicant: Rambus Inc.

Inventor： Pravin Kumar Venkatesan ,  Liji Gopalakrishnan ,  Kashinath Ullhas Prabhu ,  Makarand Ajit Shirasgaonkar

IPC: G06F13/16

Abstract: A single-ended receiver is coupled to an input-output (I/O) pin of a command and address (CA) bus. The receiver is configurable with dual-mode I/O support to operate the CA bus in a low-swing mode and a high-swing mode. The receiver is configurable to receive a first command on the I/O pin while in the high-swing mode, initiate calibration of the slave device to operate in the low-swing mode in response to the first command, switch the slave device to operate in the low-swing mode while the CA bus remains active, and to receive a second command on the I/O pin while in the low-swing mode.

公开(公告)号：US10509741B2

公开(公告)日：2019-12-17

申请号：US16145837

申请日：2018-09-28

Applicant: Rambus Inc.

Inventor： Pravin Kumar Venkatesan ,  Liji Gopalakrishnan ,  Kashinath Ullhas Prabhu ,  Makarand Ajit Shirasgaonkar

IPC: G06F13/16

Abstract: A single-ended receiver is coupled to an input-output (I/O) pin of a command and address (CA) bus. The receiver is configurable with dual-mode I/O support to operate the CA bus in a low-swing mode and a high-swing mode. The receiver is configurable to receive a first command on the I/O pin while in the high-swing mode, initiate calibration of the slave device to operate in the low-swing mode in response to the first command, switch the slave device to operate in the low-swing mode while the CA bus remains active, and to receive a second command on the I/O pin while in the low-swing mode.

公开(公告)号：US10380056B2

公开(公告)日：2019-08-13

申请号：US15647983

申请日：2017-07-12

Applicant: Rambus Inc.

Inventor： Liji Gopalakrishnan ,  Ian Shaeffer ,  Yi Lu

IPC: G06F13/00 ,  G06F13/40 ,  G11C7/10 ,  G11C11/4093 ,  G11C11/4094 ,  G11C5/04 ,  G06F13/16 ,  G11C11/4096

Abstract: A memory device or module selects between alternative command ports. Memory systems with memory modules incorporating such memory devices support point-to-point connectivity and efficient interconnect usage for different numbers of modules. The memory devices and modules can be of programmable data widths. Devices on the same module can be configured select different command ports to facilitate memory threading. Modules can likewise be configured to select different command ports for the same purpose.