公开(公告)号：US20170186880A1

公开(公告)日：2017-06-29

申请号：US15363386

申请日：2016-11-29

Applicant: Renesas Electronics Corporation

Inventor： Tatsuo NAKAYAMA ,  Hironobu MIYAMOTO ,  Yasuhiro OKAMOTO

IPC: H01L29/786 ,  H01L29/66 ,  H01L21/30 ,  H01L29/20

CPC classification number: H01L29/78681 ,  H01L21/3006 ,  H01L29/155 ,  H01L29/2003 ,  H01L29/66522 ,  H01L29/78

Abstract: A MISFET is formed to include: a co-doped layer that is formed over a substrate and has an n-type semiconductor region and a p-type semiconductor region; and a gate electrode formed over the co-doped layer via a gate insulation film. The co-doped layer contains a larger amount of Mg, a p-type impurity, than that of Si, an n-type impurity. Accordingly, the carriers (electrons) resulting from the n-type impurities (herein, Si) in the co-doped layer are canceled by the carriers (holes) resulting from p-type impurities (herein, Mg), thereby allowing the co-doped layer to serve as the p-type semiconductor region. Mg can be inactivated by introducing hydrogen into, of the co-doped layer, a region where the n-type semiconductor region is to be formed, thereby allowing the region to serve as the n-type semiconductor region. By thus introducing hydrogen into the co-doped layer, the p-type semiconductor region and the n-type semiconductor region can be formed in the same layer.

公开(公告)号：US20160293709A1

公开(公告)日：2016-10-06

申请号：US15076753

申请日：2016-03-22

Applicant: Renesas Electronics Corporation

Inventor： Tatsuo NAKAYAMA ,  Hironobu MIYAMOTO

IPC: H01L29/201 ,  H01L21/768 ,  H01L29/423 ,  H01L23/535 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L21/76898 ,  H01L29/1087 ,  H01L29/207 ,  H01L29/34 ,  H01L29/41758 ,  H01L29/4236 ,  H01L29/452 ,  H01L29/66446 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/78

Abstract: Characteristics of a semiconductor device are improved. A semiconductor device includes a voltage clamp layer, a channel base layer, a channel layer, and a barrier layer on a substrate. A trench extends to a certain depth of the channel layer through the barrier layer. A gate electrode is disposed on a gate insulating film within the trench. A source electrode and a drain electrode are provided on the two respective sides of the gate electrode. A coupling within a through-hole that extends to the voltage clamp layer electrically couples the voltage clamp layer to the source electrode. An impurity region containing an impurity having an acceptor level deeper than that of a p-type impurity is provided under the through-hole. The voltage clamp layer decreases variations in characteristics such as threshold voltage and on resistance. The contact resistance is reduced through hopping conduction due to the impurity in the impurity region.

Abstract translation: 提高了半导体器件的特性。 半导体器件包括电压钳位层，沟道基极层，沟道层和衬底上的阻挡层。 沟槽通过阻挡层延伸到沟道层的一定深度。 栅电极设置在沟槽内的栅极绝缘膜上。 源电极和漏极设置在栅电极的两个侧面上。 延伸到电压钳位层的通孔内的耦合将电压钳位层电耦合到源电极。 在通孔下面设置含有比p型杂质更高的受体水平的杂质的杂质区域。 电压钳位层减小阈值电压和导通电阻等特性的变化。 由于杂质区域中的杂质，接触电阻由于跳跃导通而降低。

公开(公告)号：US20160233211A1

公开(公告)日：2016-08-11

申请号：US14970627

申请日：2015-12-16

Applicant: Renesas Electronics Corporation

Inventor： Yoshinao MIURA ,  Hironobu MIYAMOTO ,  Yasuhiro OKAMOTO

IPC: H01L27/06 ,  H01L29/872 ,  H01L29/778 ,  H01L29/20 ,  H01L29/205

CPC classification number: H01L27/0629 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L27/0203 ,  H01L27/0207 ,  H01L27/0605 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/7787 ,  H01L29/872 ,  H01L2224/0603 ,  H01L2224/45014 ,  H01L2224/45144 ,  H01L2224/4846 ,  H01L2224/4903 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00

Abstract: The ringing of a switching waveform of a semiconductor device is restrained. For example, an interconnect (L5) is laid which functions as a source of a power transistor (Q3) and a cathode of a diode (D4), and further functioning as a drain of a power transistor (Q4) and an anode of a diode (D3). In other words, a power transistor and a diode coupled to this power transistor in series are formed in the same semiconductor chip; and further an interconnect functioning as a drain of the power transistor and an interconnect functioning as an anode of the diode are made common to each other. This structure makes it possible to decrease a parasite inductance between the power transistor and the diode coupled to each other in series.

Abstract translation: 限制了半导体器件的开关波形的振铃。 例如，布置了互连（L5），其用作功率晶体管（Q3）的源极和二极管（D4）的阴极，并且还用作功率晶体管（Q4）的漏极和功率晶体管 二极管（D3）。 换句话说，串联在该功率晶体管上的功率晶体管和二极管形成在同一半导体芯片中; 并且另外用作功率晶体管的漏极的互连和用作二极管的阳极的互连彼此共同。 这种结构使得可以降低功率晶体管和彼此串联耦合的二极管之间的寄生电感。