公开(公告)号：US10043799B2

公开(公告)日：2018-08-07

申请号：US15407598

申请日：2017-01-17

申请人： Samsung Electronics Co., Ltd.

发明人： Jaeyoung Park ,  Sungho Kang ,  Kichul Kim ,  Sunyoung Lee ,  Han Ki Lee ,  Bonyoung Koo

IPC分类号： H01L21/336 ,  H01L21/302 ,  H01L21/461 ,  H01L27/088 ,  H01L29/34 ,  H01L29/06 ,  H01L29/08 ,  H01L21/306 ,  H01L21/8234 ,  H01L21/762 ,  H01L21/02 ,  H01L29/66 ,  H01L29/45 ,  H01L21/768 ,  H01L21/3205

CPC分类号： H01L27/0886 ,  H01L21/0206 ,  H01L21/302 ,  H01L21/306 ,  H01L21/32053 ,  H01L21/76224 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/0847 ,  H01L29/34 ,  H01L29/45 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795

摘要： A method of manufacturing a semiconductor device includes forming a first plurality of recessed regions in a substrate, the substrate having a protruded active region between the first plurality of recessed regions and the protruded active region having an upper surface and a sidewall, forming a device isolation film in the first plurality of recessed regions, the device isolation film exposing the upper surface and an upper portion of the sidewall of the protruded active region, and performing a first plasma treatment on the exposed surface of the protruded active region, wherein the plasma treatment is performed using a plasma gas containing at least one of an inert gas and a hydrogen gas in a temperature of less than or equal to about 700° C.

公开(公告)号：US20180138039A1

公开(公告)日：2018-05-17

申请号：US15576664

申请日：2016-03-24

申请人： KOREA RESEARCH INSTITUTE OF STANDARDS AND SCIENCE

发明人： Hyuksang KWON ,  Jeong Won KIM ,  Eun Seong LEE

IPC分类号： H01L21/02 ,  H01L21/428

CPC分类号： H01L21/02664 ,  H01L21/02 ,  H01L21/02521 ,  H01L21/0262 ,  H01L21/02631 ,  H01L21/205 ,  H01L21/428 ,  H01L29/24 ,  H01L29/34 ,  H01L29/78696 ,  H01L31/032 ,  H01L33/26

摘要： The present invention relates to a method of fabricating a black phosphorus thin film and a black phosphorus thin film thereof and, more particularly, to a method of fabricating a black phosphorus ultrathin film by forming the black phosphorous ultrathin film in a chamber by active oxygen and removing accompanying black phosphorus oxide film water. The black phosphorus ultrathin film has a surface that does not substantially have defects and is uniform in a large area, and has a surface roughness property of 1 nm or less, to represent a high application property to an optoelectronic device and a field effect transistor.

公开(公告)号：US09929239B2

公开(公告)日：2018-03-27

申请号：US15050867

申请日：2016-02-23

申请人： Samsung Electronics Co., Ltd.

发明人： Dong-soo Lee ,  Myoung-jae Lee ,  Seong-ho Cho ,  Mohammad Rakib Uddin ,  David Seo ,  Moon-seung Yang ,  Sang-moon Lee ,  Sung-hun Lee ,  Ji-hyun Hur ,  Eui-chul Hwang

IPC分类号： H01L29/51 ,  H01L29/34 ,  H01L29/66 ,  H01L29/20 ,  H01L21/322 ,  H01L29/78 ,  H01L21/02 ,  H01L21/28 ,  H01L29/24

CPC分类号： H01L29/34 ,  H01L21/02175 ,  H01L21/02189 ,  H01L21/02192 ,  H01L21/022 ,  H01L21/02304 ,  H01L21/28158 ,  H01L21/28264 ,  H01L21/322 ,  H01L21/3228 ,  H01L29/20 ,  H01L29/2003 ,  H01L29/24 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66522 ,  H01L29/7851

摘要： The present disclosure relates to a semiconductor device including an oxygen gettering layer between a group III-V compound semiconductor layer and a dielectric layer, and a method of fabricating the semiconductor device. The semiconductor device may include a compound semiconductor layer; a dielectric layer disposed on the compound semiconductor layer; and an oxygen gettering layer interposed between the compound semiconductor layer and the dielectric layer. The oxygen gettering layer includes a material having a higher oxygen affinity than a material of the compound semiconductor layer.

公开(公告)号：US09859295B2

公开(公告)日：2018-01-02

申请号：US15425647

申请日：2017-02-06

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Fu-Ting Sung ,  Chung-Chiang Min ,  Wei-Hang Huang ,  Shih-Chang Liu ,  Chia-Shiung Tsai

IPC分类号： H01L27/11568 ,  H01L29/49 ,  H01L29/423 ,  H01L21/28 ,  H01L21/768

CPC分类号： H01L27/11568 ,  H01L21/28 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/76805 ,  H01L23/528 ,  H01L27/11521 ,  H01L29/34 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/4916 ,  H01L29/66825 ,  H01L29/7831 ,  H01L29/788 ,  H01L29/7881 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods for forming semiconductor structures are provided. The method for forming the semiconductor structure includes forming a word line cell over a substrate and forming a dielectric layer over the word line cell. The method further includes forming a conductive layer over the dielectric layer and polishing the conductive layer until the dielectric layer is exposed. The method further includes forming an oxide layer on a top surface of the conductive layer and removing portions of the conductive layer not covered by the oxide layer to form a memory gate.

公开(公告)号：US20170373177A1

公开(公告)日：2017-12-28

申请号：US15634210

申请日：2017-06-27

申请人： Fraunhofer-Gesellschaft Zur Förderung Der Angewandten Forschung E.V.

发明人： Fouad Benkhelifa

IPC分类号： H01L29/778 ,  H01L29/417 ,  H01L29/207 ,  H01L29/10 ,  H01L29/205 ,  H01L29/20 ,  H01L29/423 ,  H01L29/34

CPC分类号： H01L29/7783 ,  H01L29/1075 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/207 ,  H01L29/34 ,  H01L29/41758 ,  H01L29/42316 ,  H01L29/432

摘要： The invention relates to a semiconductor component comprising at least one field effect transistor, said transistor comprising at least a back barrier layer, a buried layer arranged on the back barrier layer, a channel layer arranged on the buried layer, a barrier layer arranged on the channel layer, and a gate layer arranged on the barrier layer, wherein the barrier layer comprises AlzGa1-zN and wherein the buried layer comprises AlxGa1-xN and at least one dopant causing a p-type conductivity, and wherein the gate layer comprises any of GaN and/or AluInvGa1-v-uN. A field effect transistor according to the disclosure may be configured to show a gate threshold voltage which is higher than approximately 0.5 V or higher than approximately 1.0 V.

公开(公告)号：US09853086B2

公开(公告)日：2017-12-26

申请号：US15350694

申请日：2016-11-14

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Henry Litzmann Edwards ,  Toan Tran ,  Jeffrey R. Debord ,  Ashesh Parikh ,  Bradley David Sucher

IPC分类号： H01L29/66 ,  H01L27/16 ,  H01L35/04 ,  H01L21/265 ,  H01L21/8238 ,  H01L27/06 ,  H01L29/34 ,  H01L35/32 ,  H01L35/34 ,  H01L27/092

CPC分类号： H01L27/16 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/823878 ,  H01L27/0617 ,  H01L27/092 ,  H01L29/34 ,  H01L35/04 ,  H01L35/32 ,  H01L35/34

摘要： In described examples, an embedded thermoelectric device is formed by forming isolation trenches in a substrate, concurrently between CMOS transistors and between thermoelectric elements of the embedded thermoelectric device. Dielectric material is formed in the isolation trenches to provide field oxide which laterally isolates the CMOS transistors and the thermoelectric elements. Germanium is implanted into the substrate in areas for the thermoelectric elements, and the substrate is subsequently annealed, to provide a germanium density of at least 0.10 atomic percent in the thermoelectric elements between the isolation trenches. The germanium may be implanted before the isolation trenches are formed, after the isolation trenches are formed and before the dielectric material is formed in the isolation trenches, and/or after the dielectric material is formed in the isolation trenches.

公开(公告)号：US09837429B2

公开(公告)日：2017-12-05

申请号：US15348009

申请日：2016-11-10

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Yunghwan Son ,  Jaesung Sim ,  Shinhwan Kang ,  Youngwoo Park ,  Jaeduk Lee

IPC分类号： H01L27/11575 ,  H01L27/11582 ,  H01L27/11573 ,  G11C16/30 ,  H01L29/34 ,  H01L27/11526 ,  G11C5/02 ,  G11C16/04 ,  H01L27/11517 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11551

CPC分类号： H01L27/11575 ,  G11C5/025 ,  G11C16/0483 ,  G11C16/30 ,  H01L27/11517 ,  H01L27/11526 ,  H01L27/11548 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582 ,  H01L29/34

摘要： A three-dimensional (3D) semiconductor memory device that includes a peripheral logic structure including peripheral logic circuits disposed on a semiconductor substrate and a first insulation layer overlapping the peripheral logic circuits, and a plurality of memory blocks spaced apart from each other on the peripheral logic structure. At least one of the memory blocks includes a well plate electrode, a semiconductor layer in contact with a first surface of the well plate electrode, a stack structure including a plurality of electrodes vertically stacked on the semiconductor layer, and a plurality of vertical structures penetrating the stack structure and connected to the semiconductor layer.

公开(公告)号：US20170338158A1

公开(公告)日：2017-11-23

申请号：US15594073

申请日：2017-05-12

申请人： DISCO CORPORATION

发明人： Naoya Sukegawa ,  Ryohei Yokota ,  Naruto Fuwa

IPC分类号： H01L21/66 ,  H01L21/02 ,  H01L23/544

CPC分类号： H01L22/12 ,  B24B37/00 ,  H01L21/02016 ,  H01L21/02024 ,  H01L21/304 ,  H01L21/3221 ,  H01L22/24 ,  H01L23/544 ,  H01L29/34

摘要： A gettering property evaluating method for a wafer includes: a gettering layer forming step of polishing a back surface opposite to a front surface of a semiconductor wafer by use of a polishing wheel to form polishing marks on the back surface and to form a gettering layer inside the semiconductor wafer and beneath the polishing marks; an imaging step of imaging at least a unit region of the back surface formed with the polishing marks by imaging means; a counting step of counting the number of the polishing marks having a width of 10 to 500 nm present in the unit region imaged; and a comparing step of comparing the number of the polishing marks counted by the counting step with a predetermined value to determine whether or not the counted number is not less than the predetermined value.

公开(公告)号：US09748344B2

公开(公告)日：2017-08-29

申请号：US15202736

申请日：2016-07-06

申请人： CoorsTek KK

发明人： Noriko Omori ,  Hiroshi Oishi ,  Yoshihisa Abe ,  Jun Komiyama ,  Kenichi Eriguchi ,  Tomoko Watanabe

IPC分类号： H01L29/20 ,  H01L29/34 ,  H01L21/02 ,  H01L29/06

CPC分类号： H01L29/2003 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/02639 ,  H01L29/0661 ,  H01L29/34 ,  H01L29/7786

摘要： The present invention provides a nitride semiconductor substrate having an initial nitride and a nitride semiconductor sequentially stacked on one principal plane of a base substrate, wherein the nitride semiconductor substrate comprises recesses depressed from an interface between the base substrate and the initial nitride toward the base substrate along one arbitrary cross section; the recesses each have a diameter of 6 nm or more and 60 nm or less and are formed at a density of 3×108 pieces/cm2 or more and 1×1011 pieces/cm2 or less; and the recess preferably has a depth of 3 nm or more and 45 nm or less from the interface between the base substrate and the initial nitride toward the base substrate.

公开(公告)号：US20170236765A1

公开(公告)日：2017-08-17

申请号：US15383336

申请日：2016-12-19

申请人： ROHM CO., LTD.

发明人： Hiroshi TAMAGAWA ,  Yasuhiro KONDO

IPC分类号： H01L23/31 ,  H01L21/78 ,  H01L21/3065 ,  H01L21/56 ,  H01L29/34 ,  H01L23/00

CPC分类号： H01L23/3178 ,  H01L21/30655 ,  H01L21/56 ,  H01L21/78 ,  H01L23/3185 ,  H01L23/3192 ,  H01L23/562 ,  H01L24/05 ,  H01L24/13 ,  H01L29/34 ,  H01L2224/02206 ,  H01L2224/02215 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/13026 ,  H01L2224/13083 ,  H01L2224/13144 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/07025

摘要： A chip part includes a substrate that has an upper surface, a lower surface positioned on an opposite side of the upper surface, and a sidewall by which the upper surface and the lower surface are connected together and that has a plurality of concavo-convex portions formed on the sidewall from a side of the upper surface toward a side of the lower surface, a functional element formed at the side of the upper surface of the substrate, a first external electrode and a second external electrode that are arranged at the upper surface of the substrate so as to be electrically connected to the functional element, and a sidewall insulating film with which the sidewall of the substrate is coated so as to fill the plurality of concavo-convex portions formed on the sidewall of the substrate with the sidewall insulating film.