公开(公告)号：US20180151499A1

公开(公告)日：2018-05-31

申请号：US15498254

申请日：2017-04-26

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Jie CHEN ,  Hsien-Wei CHEN

IPC分类号： H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L23/498

CPC分类号： H01L23/5386 ,  H01L23/3114 ,  H01L23/49827 ,  H01L23/49894 ,  H01L23/5384 ,  H01L24/09 ,  H01L24/46 ,  H01L2224/04042 ,  H01L2224/05015 ,  H01L2224/08054 ,  H01L2224/08056 ,  H01L2224/4807 ,  H01L2224/4846

摘要： Semiconductor package structures are provided. A semiconductor package structure includes a chip, a molding material surrounding the chip, a through-via extending from a first surface to a second surface of the molding material, a first re-distribution layer (RDL) wire disposed on the second surface of the molding material and coupled to the through-via, and a second RDL wire disposed on the second surface of the molding material and parallel to the first RDL wire. The second surface is opposite to the first surface. A portion of the second RDL wire across the through-via has a first segment with a first width and a second segment with a second width different from the first width.

公开(公告)号：US09966344B2

公开(公告)日：2018-05-08

申请号：US15360562

申请日：2016-11-23

申请人： FUJI ELECTRIC CO., LTD.

发明人： Shin Soyano

IPC分类号： H01L23/00 ,  H01L23/48 ,  H01L23/047 ,  H01L23/367 ,  H01L25/07 ,  H02M7/537 ,  H02M7/00 ,  H01L25/18

CPC分类号： H01L23/562 ,  H01L23/047 ,  H01L23/367 ,  H01L23/48 ,  H01L24/48 ,  H01L24/49 ,  H01L25/072 ,  H01L25/18 ,  H01L2224/45124 ,  H01L2224/48227 ,  H01L2224/4846 ,  H01L2224/4847 ,  H01L2224/4903 ,  H01L2224/49111 ,  H01L2224/49112 ,  H01L2224/49113 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/1203 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/14253 ,  H01L2924/19107 ,  H01L2924/3511 ,  H02M7/003 ,  H02M7/537 ,  H01L2224/05599 ,  H01L2924/00

摘要： A semiconductor device includes a plurality of main terminals extending from one end of a base plate toward the other end thereof, a group of semiconductor chips on a side of higher electric potential disposed on one side of the main terminal and mounted on the base plate, and a group of semiconductor chips on a side of lower electric potential disposed on the other side of the main terminal and mounted on the base plate. The one main terminal has an extending portion extending, in a direction perpendicular to the extending direction of the main terminal, toward one of both sides of the main terminal, and two adjacent semiconductor chips in one of the group of semiconductor chips on the side of higher electric potential and the group of semiconductor chips on the side of lower electric potential are axisymmetrically disposed with respect to the extending portion.

公开(公告)号：US09748225B2

公开(公告)日：2017-08-29

申请号：US14970627

申请日：2015-12-16

申请人： Renesas Electronics Corporation

发明人： Yoshinao Miura ,  Hironobu Miyamoto ,  Yasuhiro Okamoto

IPC分类号： H01L29/20 ,  H01L29/778 ,  H01L29/872 ,  H01L27/06 ,  H01L23/00 ,  H01L27/02 ,  H01L29/205

CPC分类号： H01L27/0629 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L27/0203 ,  H01L27/0207 ,  H01L27/0605 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/7787 ,  H01L29/872 ,  H01L2224/0603 ,  H01L2224/45014 ,  H01L2224/45144 ,  H01L2224/4846 ,  H01L2224/4903 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00

摘要： The ringing of a switching waveform of a semiconductor device is restrained. For example, an interconnect (L5) is laid which functions as a source of a power transistor (Q3) and a cathode of a diode (D4), and further functioning as a drain of a power transistor (Q4) and an anode of a diode (D3). In other words, a power transistor and a diode coupled to this power transistor in series are formed in the same semiconductor chip; and further an interconnect functioning as a drain of the power transistor and an interconnect functioning as an anode of the diode are made common to each other. This structure makes it possible to decrease a parasite inductance between the power transistor and the diode coupled to each other in series.

公开(公告)号：US09659847B2

公开(公告)日：2017-05-23

申请号：US15046652

申请日：2016-02-18

申请人： NXP USA, INC.

发明人： Igor Ivanovich Blednov

IPC分类号： H01L23/48 ,  H01L23/498 ,  H01L29/78 ,  H01L21/48

CPC分类号： H01L23/49811 ,  H01L21/486 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/49844 ,  H01L23/50 ,  H01L23/66 ,  H01L24/48 ,  H01L24/49 ,  H01L25/072 ,  H01L25/16 ,  H01L29/7816 ,  H01L2223/6611 ,  H01L2223/6655 ,  H01L2223/6672 ,  H01L2223/6688 ,  H01L2224/04042 ,  H01L2224/48139 ,  H01L2224/48195 ,  H01L2224/4846 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/1033 ,  H01L2924/1305 ,  H01L2924/13051 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2224/45099 ,  H01L2224/05599

摘要： A semiconductor die comprising a terminal structure for an active power device. The terminal structure comprises a metallic layer arranged to be electrically coupled between the active power device and an external contact of an integrated circuit package, a conductive sub-structure extending in parallel with the metallic layer, and located such that, when mounted within an integrated circuit device, the conductive sub-structure lies between the metallic layer and a reference voltage plane, and interconnecting elements extending between the metallic layer and the conductive sub-structure and electrically coupling the metallic layer to the conductive sub-structure. The plurality of interconnecting elements comprise first and second interconnecting elements extending between first and second lateral end regions of the metallic layer and the conductive sub-structure respectively such that the first and second interconnecting elements are laterally spaced with respect to the direction of travel of the fundamental signal for the active power device.

公开(公告)号：US20160365333A1

公开(公告)日：2016-12-15

申请号：US15177908

申请日：2016-06-09

申请人： Infineon Technologies AG

发明人： Olaf Hohlfeld

IPC分类号： H01L25/065 ,  H01L23/373 ,  H01L23/367 ,  H01L23/498

CPC分类号： H01L25/0655 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/36 ,  H01L23/3672 ,  H01L23/3731 ,  H01L23/3735 ,  H01L23/3737 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/48227 ,  H01L2224/4846 ,  H01L2224/48472 ,  H01L2924/181 ,  H01L2924/00012

摘要： A semiconductor module includes a first semiconductor switch, a second semiconductor switch, a circuit carrier arrangement and a non-ceramic dielectric isolation layer. The first semiconductor switch and the second semiconductor switch have a first load terminal and a second load termina. The current path of the first semiconductor switch and the current path of the second semiconductor switch are electrically connected in series between a first circuit node and a second circuit node. A circuit carrier arrangement includes a dielectric first isolation carrier section, a dielectric second isolation carrier section, a first upper metallization layer, a second upper metallization layer and a third upper metallization layer, a first lower metallization layer, and a second lower metallization layer. The non-ceramic dielectric isolation layer is applied to the first lower metallization layer and the second lower metallization layer, and its underside forms a heat dissipating contact area of the semiconductor module.

摘要翻译： 半导体模块包括第一半导体开关，第二半导体开关，电路载体布置和非陶瓷介电隔离层。 第一半导体开关和第二半导体开关具有第一负载端子和第二负载端子。 第一半导体开关的电流路径和第二半导体开关的电流路径串联电连接在第一电路节点和第二电路节点之间。 电路载体布置包括电介质第一隔离载体部分，电介质第二隔离载体部分，第一上金属化层，第二上金属化层和第三上金属化层，第一下金属化层和第二下金属化层。 将非陶瓷介电隔离层施加到第一下金属化层和第二下金属化层，并且其下侧形成半导体模块的散热接触区域。

公开(公告)号：US20160225688A1

公开(公告)日：2016-08-04

申请号：US15091957

申请日：2016-04-06

申请人： FUJI ELECTRIC CO., LTD.

发明人： Takashi SAITO ,  Ryoichi KATO ,  Yoshitaka NISHIMURA ,  Fumihiko MOMOSE

IPC分类号： H01L23/367 ,  H01L21/48 ,  H01L23/498

CPC分类号： H01L23/367 ,  H01L21/4875 ,  H01L21/4882 ,  H01L23/3735 ,  H01L23/4006 ,  H01L23/49838 ,  H01L23/49861 ,  H01L23/49894 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/072 ,  H01L2224/291 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/4846 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/1203 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/19107 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device includes a plurality of semiconductor elements; insulating circuit boards each including an insulating substrate, a circuit portion on a front surface of the insulating substrate connected to one semiconductor element, and a metal portion on a rear surface of the insulating substrate; a metal plate joined to the metal portions of the plurality of insulating circuit boards; and a joint member joining the plurality of insulating circuit boards to the metal plate. The metal plate has a front surface in which the insulating circuit boards are arranged apart from each other, and a rear surface including first regions corresponding to positions of the metal portions and second regions other than the first regions. At least a part of a surface of each of the first regions has a surface work-hardened layer, and the second regions have a hardness different from that of the surface work-hardened layer.

摘要翻译： 半导体器件包括多个半导体元件; 绝缘电路板，​​每个绝缘基板包括绝缘基板，连接到一个半导体元件的绝缘基板的前表面上的电路部分和绝缘基板的后表面上的金属部分; 连接到所述多个绝缘电路板的金属部分的金属板; 以及将多个绝缘电路板接合到金属板的接合构件。 金属板具有绝缘电路板彼此分开布置的前表面，以及包括与除了第一区域之外的金属部分和第二区域的位置相对应的第一区域的后表面。 每个第一区域的表面的至少一部分具有表面加工硬化层，并且第二区域具有与表面加工硬化层的硬度不同的硬度。

公开(公告)号：US20160093594A1

公开(公告)日：2016-03-31

申请号：US14863894

申请日：2015-09-24

申请人： Renesas Electronics Corporation

发明人： Katsuhiko FUNATSU ,  Yukihiro SATO ,  Takamitsu KANAZAWA ,  Masahiro KOIDO ,  Hiroyoshi TAYA

IPC分类号： H01L25/07 ,  H01L23/00 ,  H01L23/498

CPC分类号： H01L23/49838 ,  H01L21/52 ,  H01L21/54 ,  H01L23/02 ,  H01L23/04 ,  H01L23/053 ,  H01L23/057 ,  H01L23/10 ,  H01L23/12 ,  H01L23/15 ,  H01L23/16 ,  H01L23/3735 ,  H01L23/495 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/498 ,  H01L23/49811 ,  H01L23/49844 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L25/071 ,  H01L25/072 ,  H01L29/41708 ,  H01L2224/05553 ,  H01L2224/0603 ,  H01L2224/29101 ,  H01L2224/32225 ,  H01L2224/45014 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48101 ,  H01L2224/48106 ,  H01L2224/4813 ,  H01L2224/48227 ,  H01L2224/4846 ,  H01L2224/48472 ,  H01L2224/49111 ,  H01L2224/49113 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/1304 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H02S40/32 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/014 ,  H01L2224/85399

摘要： A semiconductor device includes a plurality of metal patterns formed on a ceramic substrate, and a semiconductor chip mounted on some of the plurality of metal patterns. Also, a plurality of hollow portions are formed in peripheral portions of the plurality of metal patterns. In addition, the plurality of hollow portions are not formed in a region overlapping the semiconductor chip in the plurality of metal patterns. Furthermore, the plurality of hollow portions are provided in a plurality of metal patterns arranged at a position closest to the peripheral portion of the top surface of the ceramic substrate among the plurality of metal patterns.

摘要翻译： 半导体器件包括形成在陶瓷衬底上的多个金属图案和安装在多个金属图案中的一些上的半导体芯片。 此外，在多个金属图案的周边部分中形成多个中空部分。 此外，多个中空部分不形成在与多个金属图案中的半导体芯片重叠的区域中。 此外，多个中空部分设置在多个金属图案中，多个金属图案布置在多个金属图案中最靠近陶瓷基板的顶表面的周边部分的位置。

公开(公告)号：US20150380384A1

公开(公告)日：2015-12-31

申请号：US14797056

申请日：2015-07-10

申请人： Adventive Technology Ltd.

发明人： Richard K. Williams ,  Keng Hung Lin

IPC分类号： H01L23/00 ,  H01L21/78 ,  H01L21/3105 ,  H01L21/268 ,  H01L21/48 ,  H01L21/56

CPC分类号： H01L24/96 ,  H01L21/268 ,  H01L21/31058 ,  H01L21/4825 ,  H01L21/4828 ,  H01L21/4842 ,  H01L21/56 ,  H01L21/561 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/49513 ,  H01L23/4952 ,  H01L23/49551 ,  H01L23/49555 ,  H01L23/49562 ,  H01L23/49568 ,  H01L23/49582 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/97 ,  H01L2224/0603 ,  H01L2224/16245 ,  H01L2224/32245 ,  H01L2224/37147 ,  H01L2224/40245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4846 ,  H01L2224/48464 ,  H01L2224/49111 ,  H01L2224/49171 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/01005 ,  H01L2924/01033 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2224/05599

摘要： In the fabrication of semiconductor packages, a leadframe is formed by masking and etching a metal sheet from both sides, and a plastic block is formed over a plurality of dice attached to die pads in the leadframe. A laser beam is used to form individual plastic capsules for each package, and a second laser beam is used to singulate the packages by severing the metal conductors, tie bars and rails between the packages. A wide variety of different types of packages, from gull-wing footed packages to leadless packages, with either exposed or isolated die pads, may be fabricated merely by varying the patterns of the openings in the mask layers and the width of the plastic trenches created by the first laser beam.

摘要翻译： 在半导体封装的制造中，通过从两侧掩蔽和蚀刻金属片而形成引线框，并且在引导框架中附着到焊盘的多个裸片上形成塑料块。 激光束用于为每个封装形成单独的塑料胶囊，并且第二激光束用于通过在包装之间切断金属导体，连接条和导轨来对包装进行分割。 可以仅通过改变掩模层中的开口的图案和创建的塑料沟槽的宽度来制造各种不同类型的包装，从鸥翼底脚包装到无引线封装，具有裸露或隔离的管芯焊盘 通过第一激光束。

公开(公告)号：US20150262962A1

公开(公告)日：2015-09-17

申请号：US14435932

申请日：2012-11-21

申请人： MITSUBISHI ELECTRIC CORPORATION

发明人： Takayuki Matsumoto ,  Hirotaka Onishi ,  Masuo Koga

IPC分类号： H01L23/00 ,  H01L21/56 ,  H01L23/544 ,  H01L23/31

CPC分类号： H01L24/48 ,  H01L21/56 ,  H01L23/10 ,  H01L23/12 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/3735 ,  H01L23/49894 ,  H01L23/5386 ,  H01L23/544 ,  H01L23/60 ,  H01L24/29 ,  H01L24/32 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L25/07 ,  H01L25/072 ,  H01L25/18 ,  H01L2223/54426 ,  H01L2223/54486 ,  H01L2224/29101 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/4846 ,  H01L2224/49111 ,  H01L2224/49113 ,  H01L2224/4917 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/83132 ,  H01L2224/8513 ,  H01L2224/85132 ,  H01L2224/85801 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/20656 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/85399 ,  H01L2224/05599

摘要： A soldering portion (4) and a Ni plating mark (5) are simultaneously forming by plating on a wiring pattern (2) of an insulating substrate (1). A semiconductor chip (6) is mounted on the insulating substrate (1). A position of the insulating substrate (1) is recognized by the Ni plating mark (5) and a wire (7) is bonded to the semiconductor chip (6). An electrode (8) is joined to the soldering portion (4) by solder (9). The insulating substrate (1), the semiconductor chip (6), the wire (7), and the electrode (8) are encapsulated in an encapsulation material (13).

摘要翻译： 通过电镀在绝缘基板（1）的布线图案（2）上同时形成焊接部分（4）和镀镍标记（5）。 半导体芯片（6）安装在绝缘基板（1）上。 通过Ni电镀标记（5）识别绝缘基板（1）的位置，并且将线（7）接合到半导体芯片（6）。 电极（8）通过焊料（9）与焊接部分（4）接合。 绝缘基板（1），半导体芯片（6），导线（7）和电极（8）被封装在封装材料（13）中。

公开(公告)号：US09130095B2

公开(公告)日：2015-09-08

申请号：US13920732

申请日：2013-06-18

申请人： Samsung Electronics Co., Ltd.

发明人： Che-Heung Kim ,  Young-hun Byun ,  Seong-woon Booh

IPC分类号： H01R24/00 ,  H01L31/05

CPC分类号： H01L31/0504 ,  H01L23/3735 ,  H01L23/49811 ,  H01L24/48 ,  H01L24/49 ,  H01L25/072 ,  H01L2224/48137 ,  H01L2224/48139 ,  H01L2224/48227 ,  H01L2224/4846 ,  H01L2224/48472 ,  H01L2224/49111 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/30107 ,  Y02E10/50 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

摘要： Provided are a substrate for a power module having a uniform parallel switching characteristic and a power module including the same. The substrate for the power module includes a plurality of areas on which input terminals are mounted, an area on which an output terminal is mounted, a plurality of areas on which devices are mounted, and an area on which a plurality of control pins are mounted. The plurality of areas on which the devices are mounted are bilaterally symmetric about the area on which the plurality of control pins are mounted. The plurality of areas on which the input terminals are mounted, respectively, are provided into three areas spaced apart from each other and bilaterally symmetric to each other. The plurality of areas on which the device are mounted are bilaterally symmetric about the area on which the control pins are mounted.

摘要翻译： 提供具有均匀并联开关特性的功率模块的基板和包括该基板的功率模块。 用于功率模块的基板包括安装有输入端子的多个区域，安装有输出端子的区域，安装有设备的多个区域以及安装有多个控制引脚的区域 。 安装有这些装置的多个区域是关于多个控制销安装在其上的区域的左右对称的。 分别安装有输入端子的多个区域被设置为彼此间隔开并彼此双边对称的三个区域。 安装设备的多个区域关于安装控制销的区域是双边对称的。