公开(公告)号：US20240363415A1

公开(公告)日：2024-10-31

申请号：US18770597

申请日：2024-07-11

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ming-Yen Chiu

IPC分类号： H01L21/78 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/31 ,  H01L23/544 ,  H01L23/58

CPC分类号： H01L21/78 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/544 ,  H01L23/585 ,  H01L24/05 ,  H01L24/15 ,  H01L24/19 ,  H01L24/20 ,  H01L24/14 ,  H01L24/17 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68372 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/5448 ,  H01L2224/02331 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/0603 ,  H01L2224/12105 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/1403 ,  H01L2224/16265 ,  H01L2224/1703 ,  H01L2224/214 ,  H01L2224/81005 ,  H01L2224/94

摘要： An integrated circuit component including a semiconductor die, a plurality of conductive vias and a protection layer is provided. The semiconductor die includes an active surface and a plurality of conductive pads disposed on the active surface. The conductive vias are respectively disposed on and in contact with the conductive pads, wherein each conductive via of a first group of the conductive vias has a first maximum size, each conductive via of a second group of the conductive vias has a second maximum size, and the first maximum size is less than the second maximum size in a vertical projection on the active surface. The protection layer covers the active surface and is at least in contact with sidewalls of the conductive vias.

公开(公告)号：US20240332176A1

公开(公告)日：2024-10-03

申请号：US18192521

申请日：2023-03-29

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ching-Yu Huang ,  Ting-Chu Ko

IPC分类号： H01L23/528 ,  H01L21/768 ,  H01L23/00 ,  H01L23/522 ,  H01L27/088

CPC分类号： H01L23/5283 ,  H01L21/76898 ,  H01L23/5226 ,  H01L24/03 ,  H01L24/09 ,  H01L27/088 ,  H01L2224/0603 ,  H01L2224/06051

摘要： A method includes attaching a front-side of a first die to a wafer, the first bond pad being along a back-side of the first die, the wafer comprising a substrate and a transistor along the substrate, the transistor facing the wafer, the first die comprising: a first bond pad; a first back-side interconnect structure; a first front-side interconnect structure; a first semiconductor substrate interposed between the first back-side interconnect structure and the first front-side interconnect structure; and a first transistor along the first semiconductor substrate, the first transistor facing the front-side of the first die; forming a second bond pad over the first front-side interconnect structure; and attaching a second front-side of a second die to the second bond pad of the first die, the second die comprising a second semiconductor substrate and a second transistor, the second transistor facing the front-side of the second die.

公开(公告)号：US12107042B2

公开(公告)日：2024-10-01

申请号：US17972340

申请日：2022-10-24

申请人： Intel Corporation

发明人： Robert Starkston ,  Debendra Mallik ,  John S. Guzek ,  Chia-Pin Chiu ,  Deepak Kulkarni ,  Ravi V. Mahajan

IPC分类号： H01L23/48 ,  H01L23/00 ,  H01L23/522 ,  H01L23/538 ,  H01L25/00 ,  H01L25/065 ,  H01L21/56 ,  H01L25/18

CPC分类号： H01L23/5226 ,  H01L23/5385 ,  H01L24/06 ,  H01L24/14 ,  H01L25/0655 ,  H01L25/50 ,  H01L21/563 ,  H01L24/05 ,  H01L24/13 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/05541 ,  H01L2224/05568 ,  H01L2224/0603 ,  H01L2224/131 ,  H01L2224/1403 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/83102 ,  H01L2924/12042 ,  H01L2924/15192 ,  H01L2224/83102 ,  H01L2924/00014 ,  H01L2224/05541 ,  H01L2924/206 ,  H01L2224/131 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/00

摘要： Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.

公开(公告)号：US20240304447A1

公开(公告)日：2024-09-12

申请号：US18652013

申请日：2024-05-01

申请人： ROHM CO., LTD.

发明人： Yuki NAKANO

IPC分类号： H01L21/04 ,  H01L21/02 ,  H01L21/28 ,  H01L27/04 ,  H01L29/06 ,  H01L29/10 ,  H01L29/16 ,  H01L29/20 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L29/861 ,  H01L29/872

CPC分类号： H01L21/049 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02241 ,  H01L21/02255 ,  H01L21/02271 ,  H01L21/044 ,  H01L21/28008 ,  H01L21/28264 ,  H01L27/04 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/1602 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66045 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/66446 ,  H01L29/7806 ,  H01L29/7813 ,  H01L29/8611 ,  H01L29/872 ,  H01L2224/0603

摘要： A method for producing a semiconductor power device includes forming a gate trench from a surface of the semiconductor layer toward an inside thereof. A first insulation film is formed on the inner surface of the gate trench. The method also includes removing a part on a bottom surface of the gate trench in the first insulation film. A second insulation film having a dielectric constant higher than SiO2 is formed in such a way as to cover the bottom surface of the gate trench exposed by removing the first insulation film.

公开(公告)号：US12074132B2

公开(公告)日：2024-08-27

申请号：US17598871

申请日：2019-05-22

申请人： Mitsubishi Electric Corporation

发明人： Yo Tanaka

IPC分类号： H01L23/00 ,  H01L23/12 ,  H01L23/31 ,  H01L23/367

CPC分类号： H01L24/48 ,  H01L23/12 ,  H01L23/3121 ,  H01L23/3675 ,  H01L24/05 ,  H01L24/06 ,  H01L2224/05101 ,  H01L2224/0603 ,  H01L2224/4813 ,  H01L2224/4846

摘要： A semiconductor device includes a first circuit, a second circuit, a wiring member, and a bonding material. The wiring member is connected to one of the first circuit and the second circuit. The bonding material is connected to the other of the first circuit and the second circuit. The wiring member includes a first end, a second end, and a top. The first end and the second end are connected to one of the first circuit and the second circuit. The top is located between the first end and the second end. The top is connected to the other of the first circuit and the second circuit with the bonding material in between.

公开(公告)号：US20240274554A1

公开(公告)日：2024-08-15

申请号：US18632532

申请日：2024-04-11

申请人： NANYA TECHNOLOGY CORPORATION

发明人： TENG-YEN HUANG

IPC分类号： H01L23/00 ,  H01L25/065

CPC分类号： H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L24/02 ,  H01L2224/02372 ,  H01L2224/03001 ,  H01L2224/03011 ,  H01L2224/03452 ,  H01L2224/0361 ,  H01L2224/03622 ,  H01L2224/05018 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05186 ,  H01L2224/05193 ,  H01L2224/05546 ,  H01L2224/05559 ,  H01L2224/05647 ,  H01L2224/05657 ,  H01L2224/05676 ,  H01L2224/0568 ,  H01L2224/05684 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/06181 ,  H01L2224/06517 ,  H01L2224/08145 ,  H01L2224/08146 ,  H01L2224/80379 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/0496 ,  H01L2924/0504 ,  H01L2924/0509 ,  H01L2924/0544 ,  H01L2924/059 ,  H01L2924/30105

摘要： The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first semiconductor structure and a first connecting structure, wherein the first connecting structure includes a first connecting insulating layer positioned on the first semiconductor structure, two first conductive layers positioned in the first connecting insulating layer, and a first porous layer positioned between the two first conductive layers. A porosity of the first porous layer is between about 25% and about 100%. The first semiconductor structure includes a plurality of first composite conductive features, wherein at least one of the plurality of first composite conductive features includes a first protection liner, a first graphene liner in the first protection liner and a first core conductor in the first graphene liner.

公开(公告)号：US20240274553A1

公开(公告)日：2024-08-15

申请号：US18643474

申请日：2024-04-23

申请人： Samsung Electronics Co., Ltd.

发明人： Yukyung Park ,  Ungcheon Kim ,  Wonil Lee

IPC分类号： H01L23/00 ,  H01L21/48 ,  H01L23/48 ,  H01L23/498 ,  H01L23/544 ,  H01L25/10 ,  H01L25/18

CPC分类号： H01L24/02 ,  H01L21/486 ,  H01L23/49838 ,  H01L23/544 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L25/105 ,  H01L25/18 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/04 ,  H01L2223/54426 ,  H01L2224/0213 ,  H01L2224/02141 ,  H01L2224/02145 ,  H01L2224/0215 ,  H01L2224/03019 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/05019 ,  H01L2224/05025 ,  H01L2224/05082 ,  H01L2224/0603 ,  H01L2224/06182

摘要： An interposer according to an embodiment of the present invention includes a base layer having opposite first and second surfaces, a wiring structure on the first surface of the base layer, an interposer protective layer disposed on the second surface of the base layer and having a pad recess with a lower surface of the interposer protective layer positioned at a first vertical level and a bottom surface of the pad recess positioned at a second vertical level that is higher than the first vertical level, an interposer pad of which a portion fills the pad recess of the interposer protective layer and the remaining portion protrudes from the interposer protective layer, and an interposer through electrode extending through the base layer and the interposer protective layer to the interposer pad, the interposer through electrode electrically connecting the wiring structure to the interposer pad.

公开(公告)号：US20240258186A1

公开(公告)日：2024-08-01

申请号：US18630486

申请日：2024-04-09

申请人： Rohm Co., Ltd.

发明人： Ryotaro KAKIZAKI ,  Koshun SAITO

IPC分类号： H01L23/31 ,  H01L23/00 ,  H01L23/495

CPC分类号： H01L23/3121 ,  H01L23/49555 ,  H01L24/45 ,  H01L24/48 ,  H01L23/49513 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/46 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/06181 ,  H01L2224/29139 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/46 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49052 ,  H01L2224/49112 ,  H01L2224/73265 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/13055 ,  H01L2924/13091

摘要： A semiconductor device includes a semiconductor element, a conductor, and a sealing resin. The conductor includes a die pad, a first terminal, and a second terminal. The sealing resin covers a portion of the conductor and the semiconductor element. The sealing resin includes first, second, third and fourth resin surfaces. The die pad includes a first-lead obverse surface with the semiconductor element mounted, and a first-lead reverse surface exposed from the second resin surface. The first terminal is bent in a first sense of z direction and exposed from the third resin surface. The second terminal is bent in the first sense of z direction and exposed from the fourth resin surface. The first resin surface includes a recessed region recessed in z direction toward the second resin surface. As viewed in z direction, the recessed region overlaps with an imaginary line connecting the first terminal and the second terminal.

公开(公告)号：US20240234360A9

公开(公告)日：2024-07-11

申请号：US18454994

申请日：2023-08-24

申请人： FUJI ELECTRIC CO., LTD.

发明人： Mai SAITO ,  Daiki YOSHIDA

IPC分类号： H01L23/00 ,  H01L23/31

CPC分类号： H01L24/40 ,  H01L23/3135 ,  H01L24/05 ,  H01L24/37 ,  H01L23/3735 ,  H01L24/06 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/06181 ,  H01L2224/32225 ,  H01L2224/37012 ,  H01L2224/37147 ,  H01L2224/40227 ,  H01L2224/40991 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73221 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2924/13055 ,  H01L2924/13091

摘要： A semiconductor module includes a circuit board having a semiconductor element mounted thereon, a lead including a first bonding portion bonded to the semiconductor element via a bonding material and a wiring portion connected to the first bonding portion, and a sealing material that seals the semiconductor element and the lead. The first bonding portion has first and second side surfaces that face each other. The wiring portion has a bent portion connected to the first bonding portion at a side of the first bonding portion at which the first side surface is located. The bent portion is bent at a border between the first bonding portion and the bent portion in a direction away from a lower surface of the first bonding portion. The border is located between the first and second side surfaces of the first bonding portion in a plan view of the lead.

公开(公告)号：US20240222303A1

公开(公告)日：2024-07-04

申请号：US18226589

申请日：2023-07-26

申请人： Samsung Electronics Co., Ltd.

发明人： Daehyun KIM ,  KUNSIL LEE

IPC分类号： H01L23/00 ,  H01L23/498

CPC分类号： H01L24/14 ,  H01L23/49811 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/13 ,  H01L24/16 ,  H01L24/11 ,  H01L24/17 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L24/81 ,  H01L25/18 ,  H01L2224/05073 ,  H01L2224/05144 ,  H01L2224/05555 ,  H01L2224/0557 ,  H01L2224/05573 ,  H01L2224/05647 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/0613 ,  H01L2224/06181 ,  H01L2224/08145 ,  H01L2224/08225 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/13007 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/1413 ,  H01L2224/16105 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81815

摘要： Disclosed are semiconductor packages and their fabrication methods. The semiconductor package comprises a first substrate having first pads on a first surface of the first substrate, a second substrate on the first substrate and having a plurality of second pads on a second surface of the second substrate, and connection terminals between the first substrate and the second substrate and correspondingly coupling the first pad to the second pads. Each of the connection terminals has a first major axis and a first minor axis that are parallel to the first surface of the first substrate and are orthogonal to each other. When viewed in a plan view, the first minor axis of each of the connection terminals is directed toward a center of the first substrate.