公开(公告)号：US10552058B1

公开(公告)日：2020-02-04

申请号：US15211927

申请日：2016-07-15

申请人： Radian Memory Systems, Inc.

发明人： Mike Jadon ,  Craig Robertson ,  Robert Lercari

IPC分类号： G06F3/06

摘要： Processing functions are offloaded to a memory controller for nonvolatile memory by a host in connection with write data. The nonvolatile memory executes these functions, producing processed data that must be written into memory; for example, the offloaded functions can include erasure coding, with the nonvolatile memory controller generating redundancy information that must be written into memory. The memory controller holds this information in internal RAM and then later writes this information into nonvolatile memory according to dynamically determined write time and/or destinations selected by the host, so as to not collide with host data access requests. In one embodiment, the memory is NAND flash memory and the memory controller is a cooperative memory controller that permits the host to schedule concurrent operations in respective, configurable virtual block devices which have been configured by the host out of a pool of structural flash memory structures managed by the memory controller.

公开(公告)号：US11914523B1

公开(公告)日：2024-02-27

申请号：US18140938

申请日：2023-04-28

申请人： Radian Memory Systems, Inc.

发明人： Robert Lercari ,  Alan Chen ,  Mike Jadon ,  Craig Robertson ,  Andrey V. Kuzmin

IPC分类号： G06F12/1009 ,  G06F12/02 ,  G06F3/06 ,  G06F12/109

CPC分类号： G06F12/1009 ,  G06F3/064 ,  G06F3/0616 ,  G06F3/0688 ,  G06F12/0246 ,  G06F12/109 ,  G06F3/0659 ,  G06F3/0662 ,  G06F2212/1016 ,  G06F2212/7201 ,  G06F2212/7202 ,  G06F2212/7205

摘要： This disclosure provides techniques hierarchical address virtualization within a memory controller and configurable block device allocation. By performing address translation only at select hierarchical levels, a memory controller can be designed to have predictable I/O latency, with brief or otherwise negligible logical-to-physical address translation time. In one embodiment, address transition may be implemented entirely with logical gates and look-up tables of a memory controller integrated circuit, without requiring processor cycles. The disclosed virtualization scheme also provides for flexibility in customizing the configuration of virtual storage devices, to present nearly any desired configuration to a host or client.

公开(公告)号：US11740801B1

公开(公告)日：2023-08-29

申请号：US17568891

申请日：2022-01-05

申请人： Radian Memory Systems, Inc.

发明人： Andrey V. Kuzmin ,  Alan Chen ,  Robert Lercari

IPC分类号： G06F3/06 ,  G06F12/02

CPC分类号： G06F3/0616 ,  G06F3/0647 ,  G06F3/0679 ,  G06F12/0246 ,  G06F2212/7205 ,  G06F2212/7211

摘要： This disclosure provides techniques for managing memory which match per-data metrics to those of other data or to memory destination. In one embodiment, wear data is tracked for at least one tier of nonvolatile memory (e.g., flash memory) and a measure of data persistence (e.g., age, write frequency, etc.) is generated or tracked for each data item. Memory wear management based on these individually-generated or tracked metrics is enhanced by storing or migrating data in a manner where persistent data is stored in relatively worn memory locations (e.g., relatively more-worn flash memory) while temporary data is stored in memory that is less worn or is less susceptible to wear. Other data placement or migration techniques are also disclosed.

公开(公告)号：US11449240B1

公开(公告)日：2022-09-20

申请号：US17240788

申请日：2021-04-26

申请人： Radian Memory Systems, Inc.

发明人： Mike Jadon ,  Craig Robertson ,  Robert Lercari

IPC分类号： G06F3/06 ,  G06F11/10

摘要： Processing functions are offloaded to a memory controller for nonvolatile memory by a host in connection with write data. The nonvolatile memory executes these functions, producing processed data that must be written into memory; for example, the offloaded functions can include erasure coding, with the nonvolatile memory controller generating redundancy information that must be written into memory. The memory controller holds this information in internal RAM and then later writes this information into nonvolatile memory according to dynamically determined write time and/or destinations selected by the host, so as to not collide with host data access requests. In one embodiment, the memory is NAND flash memory and the memory controller is a cooperative memory controller that permits the host to schedule concurrent operations in respective, configurable virtual block devices which have been configured by the host out of a pool of structural flash memory structures managed by the memory controller.

公开(公告)号：US11360909B1

公开(公告)日：2022-06-14

申请号：US16997394

申请日：2020-08-19

申请人： Radian Memory Systems, Inc.

发明人： Robert Lercari ,  Alan Chen ,  Mike Jadon ,  Craig Robertson ,  Andrey V. Kuzmin

IPC分类号： G06F12/1009 ,  G06F3/06 ,  G06F12/109 ,  G06F12/02

摘要： This disclosure provides techniques hierarchical address virtualization within a memory controller and configurable block device allocation. By performing address translation only at select hierarchical levels, a memory controller can be designed to have predictable I/O latency, with brief or otherwise negligible logical-to-physical address translation time. In one embodiment, address transition may be implemented entirely with logical gates and look-up tables of a memory controller integrated circuit, without requiring processor cycles. The disclosed virtualization scheme also provides for flexibility in customizing the configuration of virtual storage devices, to present nearly any desired configuration to a host or client.

公开(公告)号：US11347657B1

公开(公告)日：2022-05-31

申请号：US17479475

申请日：2021-09-20

申请人： Radian Memory Systems, Inc.

发明人： Robert Lercari ,  Alan Chen ,  Mike Jadon ,  Craig Robertson ,  Andrey V. Kuzmin

IPC分类号： G06F12/1009 ,  G06F3/06 ,  G06F12/109 ,  G06F12/02

摘要： This disclosure provides techniques hierarchical address virtualization within a memory controller and configurable block device allocation. By performing address translation only at select hierarchical levels, a memory controller can be designed to have predictable I/O latency, with brief or otherwise negligible logical-to-physical address translation time. In one embodiment, address transition may be implemented entirely with logical gates and look-up tables of a memory controller integrated circuit, without requiring processor cycles. The disclosed virtualization scheme also provides for flexibility in customizing the configuration of virtual storage devices, to present nearly any desired configuration to a host or client.

公开(公告)号：US11321237B1

公开(公告)日：2022-05-03

申请号：US16779906

申请日：2020-02-03

申请人： Radian Memory Systems, Inc.

发明人： Robert Lercari ,  Alan Chen ,  Mike Jadon ,  Craig Robertson ,  Andrey V. Kuzmin

IPC分类号： G06F12/1009 ,  G06F3/06 ,  G06F12/109 ,  G06F12/02

摘要： This disclosure provides techniques hierarchical address virtualization within a memory controller and configurable block device allocation. By performing address translation only at select hierarchical levels, a memory controller can be designed to have predictable I/O latency, with brief or otherwise negligible logical-to-physical address translation time. In one embodiment, address transition may be implemented entirely with logical gates and look-up tables of a memory controller integrated circuit, without requiring processor cycles. The disclosed virtualization scheme also provides for flexibility in customizing the configuration of virtual storage devices, to present nearly any desired configuration to a host or client.

公开(公告)号：US11275695B1

公开(公告)日：2022-03-15

申请号：US16794892

申请日：2020-02-19

申请人： Radian Memory Systems, Inc.

发明人： Robert Lercari ,  Alan Chen ,  Mike Jadon ,  Craig Robertson ,  Andrey V. Kuzmin

IPC分类号： G06F12/1009 ,  G06F3/06 ,  G06F12/109 ,  G06F12/02

摘要： This disclosure provides techniques hierarchical address virtualization within a memory controller and configurable block device allocation. By performing address translation only at select hierarchical levels, a memory controller can be designed to have predictable I/O latency, with brief or otherwise negligible logical-to-physical address translation time. In one embodiment, address transition may be implemented entirely with logical gates and look-up tables of a memory controller integrated circuit, without requiring processor cycles. The disclosed virtualization scheme also provides for flexibility in customizing the configuration of virtual storage devices, to present nearly any desired configuration to a host or client.

公开(公告)号：US11221960B1

公开(公告)日：2022-01-11

申请号：US16808317

申请日：2020-03-03

申请人： Radian Memory Systems, Inc.

发明人： Robert Lercari ,  Alan Chen ,  Mike Jadon ,  Craig Robertson ,  Andrey V. Kuzmin

IPC分类号： G06F12/1009 ,  G06F3/06 ,  G06F12/109 ,  G06F12/02

摘要： This disclosure provides techniques hierarchical address virtualization within a memory controller and configurable block device allocation. By performing address translation only at select hierarchical levels, a memory controller can be designed to have predictable I/O latency, with brief or otherwise negligible logical-to-physical address translation time. In one embodiment, address transition may be implemented entirely with logical gates and look-up tables of a memory controller integrated circuit, without requiring processor cycles. The disclosed virtualization scheme also provides for flexibility in customizing the configuration of virtual storage devices, to present nearly any desired configuration to a host or client.

公开(公告)号：US11086789B1

公开(公告)日：2021-08-10

申请号：US17213015

申请日：2021-03-25

申请人： Radian Memory Systems, Inc.

发明人： Robert Lercari ,  Alan Chen ,  Mike Jadon ,  Craig Robertson ,  Andrey V. Kuzmin

IPC分类号： G06F12/1009 ,  G06F3/06 ,  G06F12/02 ,  G06F12/109

摘要： This disclosure provides techniques hierarchical address virtualization within a memory controller and configurable block device allocation. By performing address translation only at select hierarchical levels, a memory controller can be designed to have predictable I/O latency, with brief or otherwise negligible logical-to-physical address translation time. In one embodiment, address transition may be implemented entirely with logical gates and look-up tables of a memory controller integrated circuit, without requiring processor cycles. The disclosed virtualization scheme also provides for flexibility in customizing the configuration of virtual storage devices, to present nearly any desired configuration to a host or client.