公开(公告)号：US11347658B1

公开(公告)日：2022-05-31

申请号：US17513776

申请日：2021-10-28

申请人： Radian Memory Systems, Inc.

发明人： Robert Lercari ,  Alan Chen ,  Mike Jadon ,  Craig Robertson ,  Andrey V. Kuzmin

IPC分类号： G06F12/1009 ,  G06F3/06 ,  G06F12/109 ,  G06F12/02

摘要： This disclosure provides techniques hierarchical address virtualization within a memory controller and configurable block device allocation. By performing address translation only at select hierarchical levels, a memory controller can be designed to have predictable I/O latency, with brief or otherwise negligible logical-to-physical address translation time. In one embodiment, address transition may be implemented entirely with logical gates and look-up tables of a memory controller integrated circuit, without requiring processor cycles. The disclosed virtualization scheme also provides for flexibility in customizing the configuration of virtual storage devices, to present nearly any desired configuration to a host or client.

公开(公告)号：US11347656B1

公开(公告)日：2022-05-31

申请号：US17479444

申请日：2021-09-20

申请人： Radian Memory Systems, Inc.

发明人： Robert Lercari ,  Alan Chen ,  Mike Jadon ,  Craig Robertson ,  Andrey V. Kuzmin

IPC分类号： G06F12/1009 ,  G06F3/06 ,  G06F12/109 ,  G06F12/02

摘要： This disclosure provides techniques hierarchical address virtualization within a memory controller and configurable block device allocation. By performing address translation only at select hierarchical levels, a memory controller can be designed to have predictable I/O latency, with brief or otherwise negligible logical-to-physical address translation time. In one embodiment, address transition may be implemented entirely with logical gates and look-up tables of a memory controller integrated circuit, without requiring processor cycles. The disclosed virtualization scheme also provides for flexibility in customizing the configuration of virtual storage devices, to present nearly any desired configuration to a host or client.

公开(公告)号：US11080181B1

公开(公告)日：2021-08-03

申请号：US17211482

申请日：2021-03-24

申请人： Radian Memory Systems, Inc.

发明人： Andrey V. Kuzmin ,  Mike Jadon ,  Richard M. Mathews

IPC分类号： G06F12/02

摘要： This disclosure provides for host-controller cooperation in managing NAND flash memory. The controller maintains information for each erase unit which tracks memory usage. This information assists the host in making decisions about specific operations, for example, initiating garbage collection, space reclamation, wear leveling or other operations. For example, metadata can be provided to the host identifying whether each page of an erase unit has been released, and the host can specifically then command each of consolidation and erase using direct addressing. By redefining host-controller responsibilities in this manner, much of the overhead association with FTL functions can be substantially removed from the memory controller, with the host directly specifying physical addresses. This reduces performance unpredictability and overhead, thereby facilitating integration of solid state drives (SSDs) with other forms of storage. The disclosed techniques are especially useful for direct-attached and/or network-attached storage.

公开(公告)号：US11048643B1

公开(公告)日：2021-06-29

申请号：US16808320

申请日：2020-03-03

申请人： Radian Memory Systems, Inc.

发明人： Robert Lercari ,  Alan Chen ,  Mike Jadon ,  Craig Robertson ,  Andrey V. Kuzmin

IPC分类号： G06F12/1009 ,  G06F3/06 ,  G06F12/109 ,  G06F12/02

摘要： This disclosure provides techniques hierarchical address virtualization within a memory controller and configurable block device allocation. By performing address translation only at select hierarchical levels, a memory controller can be designed to have predictable I/O latency, with brief or otherwise negligible logical-to-physical address translation time. In one embodiment, address transition may be implemented entirely with logical gates and look-up tables of a memory controller integrated circuit, without requiring processor cycles. The disclosed virtualization scheme also provides for flexibility in customizing the configuration of virtual storage devices, to present nearly any desired configuration to a host or client.

公开(公告)号：US11023387B1

公开(公告)日：2021-06-01

申请号：US16783100

申请日：2020-02-05

申请人： Radian Memory Systems, Inc.

发明人： Robert Lercari ,  Alan Chen ,  Mike Jadon ,  Craig Robertson ,  Andrey V. Kuzmin

IPC分类号： G06F12/1009 ,  G06F3/06 ,  G06F12/109 ,  G06F12/02

摘要： This disclosure provides techniques hierarchical address virtualization within a memory controller and configurable block device allocation. By performing address translation only at select hierarchical levels, a memory controller can be designed to have predictable I/O latency, with brief or otherwise negligible logical-to-physical address translation time. In one embodiment, address transition may be implemented entirely with logical gates and look-up tables of a memory controller integrated circuit, without requiring processor cycles. The disclosed virtualization scheme also provides for flexibility in customizing the configuration of virtual storage devices, to present nearly any desired configuration to a host or client.

公开(公告)号：US10884915B1

公开(公告)日：2021-01-05

申请号：US15625956

申请日：2017-06-16

申请人： Radian Memory Systems, Inc.

发明人： Andrey V. Kuzmin ,  Mike Jadon ,  Richard M. Mathews

IPC分类号： G06F12/02

摘要： This disclosure provides for host-controller cooperation in managing NAND flash memory. The controller maintains information for each erase unit which tracks memory usage. This information assists the host in making decisions about specific operations, for example, initiating garbage collection, space reclamation, wear leveling or other operations. For example, metadata can be provided to the host identifying whether each page of an erase unit has been released, and the host can specifically then command each of consolidation and erase using direct addressing. By redefining host-controller responsibilities in this manner, much of the overhead association with FTL functions can be substantially removed from the memory controller, with the host directly specifying physical addresses. This reduces performance unpredictability and overhead, thereby facilitating integration of solid state drives (SSDs) with other forms of storage. The disclosed techniques are especially useful for direct-attached and/or network-attached storage.

公开(公告)号：US10552085B1

公开(公告)日：2020-02-04

申请号：US15211939

申请日：2016-07-15

申请人： Radian Memory Systems, Inc.

发明人： Alan Chen ,  Craig Robertson ,  Robert Lercari ,  Andrey V. Kuzmin

IPC分类号： G06F3/06

摘要： A host stores “context” metadata for logical block addresses (LBAs) in a manner tied to physical location. Notwithstanding log-structured or copy on write processes, the host is then provided with immediate context when the host is called upon to assist a memory controller with data identified by physical location, for example, for memory reconfiguration, garbage collection, wear leveling or other processes. The metadata for example can provide the host with insight as to which data may be moved to enhance performance optimization and where that data can be placed. In one embodiment, the host writes back one or more references that span multiple layers of indirection in concert with write of the underlying data; in another embodiment, the context can point to other metadata.

公开(公告)号：US11972153B1

公开(公告)日：2024-04-30

申请号：US18097024

申请日：2023-01-13

申请人： Radian Memory Systems, Inc.

发明人： Robert Lercari ,  Mike Jadon ,  Andrey V. Kuzmin

IPC分类号： G06F3/06 ,  G06F12/10

CPC分类号： G06F3/0659 ,  G06F3/0604 ,  G06F3/0679 ,  G06F12/10 ,  G06F2212/657

摘要： This disclosure provides techniques for managing writes of data useful for storage systems that do not permit overwrite of a logical address. One implementation provides a nonvolatile memory storage drive, such as a flash memory drive, that provides support for zoned drive and/or Open Channel-compliant architectures. Circuitry on the storage drive tracks storage location release metadata for addressable memory space, optionally providing to a host system information upon which maintenance decisions or related scheduling can be based. The storage drive can also provide buffering support for accommodating receipt of out-of-order writes and unentanglement and performance of out of order writes, with buffering resources being configurable according to any one of a number of parameters. The disclosed storage drive facilitates reduced error rates and lower request traffic in a manner consistent with newer memory standards that mandate that writes to logical addresses be sequential.

公开(公告)号：US11907134B1

公开(公告)日：2024-02-20

申请号：US17469758

申请日：2021-09-08

申请人： Radian Memory Systems, Inc.

发明人： Robert Lercari ,  Alan Chen ,  Mike Jadon ,  Craig Robertson ,  Andrey V. Kuzmin

IPC分类号： G06F12/1009 ,  G06F12/02 ,  G06F3/06 ,  G06F12/109

CPC分类号： G06F12/1009 ,  G06F3/064 ,  G06F3/0616 ,  G06F3/0688 ,  G06F12/0246 ,  G06F12/109 ,  G06F3/0659 ,  G06F3/0662 ,  G06F2212/1016 ,  G06F2212/7201 ,  G06F2212/7202 ,  G06F2212/7205

摘要： This disclosure provides techniques hierarchical address virtualization within a memory controller and configurable block device allocation. By performing address translation only at select hierarchical levels, a memory controller can be designed to have predictable I/O latency, with brief or otherwise negligible logical-to-physical address translation time. In one embodiment, address transition may be implemented entirely with logical gates and look-up tables of a memory controller integrated circuit, without requiring processor cycles. The disclosed virtualization scheme also provides for flexibility in customizing the configuration of virtual storage devices, to present nearly any desired configuration to a host or client.

公开(公告)号：US11748257B1

公开(公告)日：2023-09-05

申请号：US17931516

申请日：2022-09-12

申请人： Radian Memory Systems, Inc.

发明人： Andrey V. Kuzmin ,  James G. Wayda

IPC分类号： G06F12/02 ,  G06F12/10 ,  G06F16/18 ,  G06F11/10 ,  G06F3/06 ,  G06F8/654 ,  G06F15/76

CPC分类号： G06F12/0246 ,  G06F3/0611 ,  G06F3/0638 ,  G06F3/0679 ,  G06F3/0688 ,  G06F8/654 ,  G06F11/1068 ,  G06F11/1072 ,  G06F12/10 ,  G06F16/1847 ,  G06F2015/766 ,  G06F2212/2022 ,  G06F2212/7207 ,  G06F2212/7208

摘要： This disclosure provides for improvements in managing multi-drive, multi-die or multi-plane NAND flash memory. In one embodiment, the host directly assigns physical addresses and performs logical-to-physical address translation in a manner that reduces or eliminates the need for a memory controller to handle these functions, and initiates functions such as wear leveling in a manner that avoids competition with host data accesses. A memory controller optionally educates the host on array composition, capabilities and addressing restrictions. Host software can therefore interleave write and read requests across dies in a manner unencumbered by memory controller address translation. For multi-plane designs, the host writes related data in a manner consistent with multi-plane device addressing limitations. The host is therefore able to “plan ahead” in a manner supporting host issuance of true multi-plane read commands.