公开(公告)号：US08384429B2

公开(公告)日：2013-02-26

申请号：US12761812

申请日：2010-04-16

申请人： Berndt Gammel ,  Thomas Nirschl ,  Gerd Dirscherl ,  Philip Schlazer ,  Stefan Rueping

发明人： Berndt Gammel ,  Thomas Nirschl ,  Gerd Dirscherl ,  Philip Schlazer ,  Stefan Rueping

IPC分类号： H03K19/20

CPC分类号： H03K19/20 ,  G11C13/0004 ,  H01L27/24

摘要： An integrated circuit has one or more logic gates and a control circuit. The control circuit has one or more control elements coupled to the logic gates. The control circuit controls the states of the one or more logic gates. The one or more control elements have one or more programmable resistance elements and/or one or more threshold switching elements.

摘要翻译： 集成电路具有一个或多个逻辑门和控制电路。 控制电路具有耦合到逻辑门的一个或多个控制元件。 控制电路控制一个或多个逻辑门的状态。 一个或多个控制元件具有一个或多个可编程电阻元件和/或一个或多个阈值开关元件。

公开(公告)号：US07982488B2

公开(公告)日：2011-07-19

申请号：US12474648

申请日：2009-05-29

申请人： Thomas Nirschl ,  Berndt Gammel ,  Stefan Rueping ,  Ronald Kakoschke ,  Gerd Dirscherl ,  Philip Schlazer

发明人： Thomas Nirschl ,  Berndt Gammel ,  Stefan Rueping ,  Ronald Kakoschke ,  Gerd Dirscherl ,  Philip Schlazer

IPC分类号： H03K19/00 ,  G11C11/34

CPC分类号： G11C13/0004 ,  G11C13/0059 ,  G11C2213/71 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/1233

摘要： A semiconductor chip having a subcircuit formed in a substrate; and a phase-change memory cell located on the subcircuit, and configured to directly detect an attack on the subcircuit, or to form a shield to prevent physical access to the subcircuit.

摘要翻译： 一种半导体芯片，其具有在基板中形成的子电路; 以及位于子电路上的相变存储器单元，并且被配置为直接检测对子电路的攻击，或者形成屏蔽以防止物理访问子电路。

公开(公告)号：US08159857B2

公开(公告)日：2012-04-17

申请号：US12563427

申请日：2009-09-21

申请人： Berndt Gammel ,  Thomas Nirschl ,  Gerd Dirscherl ,  Philip Schlazer

发明人： Berndt Gammel ,  Thomas Nirschl ,  Gerd Dirscherl ,  Philip Schlazer

IPC分类号： G11C11/00

CPC分类号： G11C13/0059 ,  G11C13/0004 ,  G11C13/0069

摘要： One or more embodiments relate to an electronic device comprising a circuitry and a programmable resistive element. The programmable resistive element comprises a first and a second state, wherein the programmable resistive element is configured to allow switching from the second state into the first state in response to a signal comprising at least a predefined level. The circuitry is configured to provide signals up the predefined level, wherein the circuitry is configured to provide a switch signal to the programmable resistive element, wherein the switch signal causes switching from the first into the second state.

摘要翻译： 一个或多个实施例涉及包括电路和可编程电阻元件的电子设备。 可编程电阻元件包括第一和第二状态，其中可编程电阻元件被配置为允许响应于包括至少预定义电平的信号从第二状态切换到第一状态。 该电路被配置为提供上述预定义电平的信号，其中电路被配置为向可编程电阻元件提供开关信号，其中开关信号引起从第一状态切换到第二状态。

公开(公告)号：US08074081B2

公开(公告)日：2011-12-06

申请号：US10966847

申请日：2004-10-15

申请人： Berndt Gammel

发明人： Berndt Gammel

IPC分类号： G06F11/30 ,  G06F12/14

CPC分类号： G06Q20/367 ,  G06F12/121 ,  G06F21/755 ,  G06Q20/105 ,  G06Q20/3672 ,  G06Q30/018

摘要： A data storage device includes a plurality of data storage units, a physical random number generator with a noise source based on a physical noise process, for generating a random number, and a replacer for selecting a data storage unit wherein data is to be stored, depending on the random number. Selecting, on the basis of genuine random numbers, data storage units and/or lines to be replaced in the cache.

摘要翻译： 数据存储装置包括多个数据存储单元，具有用于生成随机数的基于物理噪声处理的噪声源的物理随机数发生器，以及用于选择要存储数据的数据存储单元的替换器， 取决于随机数。 根据真正的随机数，在缓存中选择要替换的数据存储单元和/或行。

公开(公告)号：US07836234B2

公开(公告)日：2010-11-16

申请号：US11958511

申请日：2007-12-18

申请人： Stefan Erdmenger ,  Berndt Gammel ,  Josef Riegebauer ,  Till Winteler

发明人： Stefan Erdmenger ,  Berndt Gammel ,  Josef Riegebauer ,  Till Winteler

IPC分类号： G06F13/00 ,  G06F3/00 ,  G06F1/00

CPC分类号： H04L12/403 ,  G06K7/10247 ,  H04L43/00 ,  H04L69/28

摘要： A communication apparatus for communication according to a master-slave communication protocol is formed as a slave instance communicating with a master instance via a bus. The master instance is operative to switch the bus into a bus suspend state if no bus activity is present during a predetermined interval. In response to a bus suspend state, the slave instance makes a transition to a slave suspend state. The communication apparatus includes a monitor configured to monitor the bus activity and a transmitter configured to transmit a signal via the bus if the monitor does not recognize any bus activity during part of the predetermined interval and a transition of the slave instance to the slave suspend state is undesirable, wherein the signal is operative to prevent the master instance from switching the bus into the bus suspend state.

摘要翻译： 根据主 - 从通信协议进行通信的通信装置形成为通过总线与主实例进行通信的从属实例。 如果在预定间隔期间没有总线活动，则主机实例用于将总线切换到总线挂起状态。 响应于总线挂起状态，从站实例转换到从站挂起状态。 通信装置包括：监视器，其被配置为监视总线活动;以及发射器，被配置为在所述预定间隔的一部分期间监视器不识别任何总线活动以及从属实例到从属暂停状态的转变时经由总线发送信号 是不希望的，其中信号可操作以防止主机实例将总线切换到总线挂起状态。

公开(公告)号：US07124275B2

公开(公告)日：2006-10-17

申请号：US10480081

申请日：2002-05-14

申请人： Berndt Gammel ,  Christian May ,  Ralph Ledwa ,  Holger Sedlak

发明人： Berndt Gammel ,  Christian May ,  Ralph Ledwa ,  Holger Sedlak

IPC分类号： G06F12/00

CPC分类号： G06F12/1009 ,  G06F2212/651 ,  G06F2212/681

摘要： A method for determining a physical address from a virtual address, wherein a mapping regulation between the virtual address and the physical address is implemented as hierarchical tree structure with compressed nodes. First, a compression indicator included in the mapping regulation is read, and a portion of the virtual address associated with the considered node level is read. Using the compression indicator and the portion of the virtual address, an entry in the node list of the considered node is determined. The determined entry is read, whereupon the physical address can be determined directly, if the considered node level has been the hierarchically lowest node level. If higher node levels to be processed are present, the previous steps in determining the physical address for compressed nodes of lower hierarchy level are repeated until the hierarchically lowest node level is reached.

摘要翻译： 一种用于从虚拟地址确定物理地址的方法，其中虚拟地址和物理地址之间的映射调节被实现为具有压缩节点的分层树结构。 首先，读取包含在映射规则中的压缩指示符，并且读取与所考虑的节点级别相关联的虚拟地址的一部分。 使用压缩指示符和虚拟地址的一部分，确定所考虑节点的节点列表中的条目。 读取确定的条目，从而可以直接确定物理地址，如果所考虑的节点级别是层次最低的节点级别。 如果存在要处理的较高节点级别，则重复确定较低层次级别的压缩节点的物理地址的先前步骤，直到达到分级最低节点级别。

公开(公告)号：US20060200514A1

公开(公告)日：2006-09-07

申请号：US11187039

申请日：2005-07-20

申请人： Wieland Fischer ,  Berndt Gammel

发明人： Wieland Fischer ,  Berndt Gammel

IPC分类号： G06F7/38

CPC分类号： G06F7/38 ,  G06F21/75 ,  G06F2207/7223 ,  G06F2207/7266

摘要： An apparatus for calculating a representation of a result operand of the non-linear logical operation between a first operand and a second operand includes a first logic gate and a second logic gate. Each operand is represented by two auxiliary operands, which, when linearly combined together result in the respective operand. The first and second logic gates are designed such that an average energy consumption of the first or second logic gate is substantially equal to a plurality of combinations of auxiliary operands at the beginning of a first operation cycle and auxiliary operands at the beginning of a second operating cycle, the average energy being derivable from a plurality of different orders of occurrences of the first to fourth auxiliary operands.

公开(公告)号：US20060101513A1

公开(公告)日：2006-05-11

申请号：US11221383

申请日：2005-09-06

申请人： Berndt Gammel ,  Steffen Sonnekalb

发明人： Berndt Gammel ,  Steffen Sonnekalb

IPC分类号： G06F7/38

CPC分类号： G06F21/755

摘要： A method for operating a microprocessor in which there is at least one program branch and/or program delay which is implemented under random-bit control and as a hardware-based command in order to modulate a program flow and which ensures that every pass through a particular program brings about a respective program execution time which is different than that in preceding program passes.

摘要翻译： 一种用于操作微处理器的方法，其中存在至少一个在随机位控制下实现的程序分支和/或程序延迟，以及作为基于硬件的命令，以便调制程序流程，并且确保每次通过一个 特定程序带来与前面的程序通过不同的程序执行时间。

公开(公告)号：US20050041810A1

公开(公告)日：2005-02-24

申请号：US10893161

申请日：2004-07-16

申请人： Berndt Gammel ,  Franz Klug ,  Oliver Kniffler

发明人： Berndt Gammel ,  Franz Klug ,  Oliver Kniffler

IPC分类号： G06F5/01 ,  G06F21/72 ,  H04K1/00

CPC分类号： G06F5/01 ,  G06F21/72 ,  G06F2207/7219

摘要： A shift device for shifting a first place of a data word, which consists of a plurality of places, to a second place so as to obtain a shifted data word, wherein the first place is encrypted using a first encryption parameter and wherein the second place is encrypted using a second encryption parameter, includes a unit for shifting the first place of the data word to the second place of the data word, a unit for re-encrypting the first place from an encryption using the first encryption parameter into an encryption using the second encryption pa- rameter, and a control for controlling the unit for shifting and the unit for re-encryption so that the first place is first shifted to the second place and is then re-encrypted, or that the first place is first re-encrypted and is then shifted to the second place. This ensures that data encrypted either with the first encryption parameter or with the second encryption parameter are always shifted, thus making it harder for attackers to eavesdrop on clear text data.

摘要翻译： 一种移位装置，用于将由多个位置组成的数据字的第一位移动到第二位置，以便获得移位的数据字，其中，使用第一加密参数对第一位置进行加密，并且其中第二位置 使用第二加密参数加密，包括用于将数据字的第一位移动到数据字的第二位的单元，用于使用第一加密参数从加密重新加密第一位的单元到使用 第二加密参数，以及用于控制用于移位的单元和用于重新加密的单元的控制，使得第一位置首先被移动到第二位置，然后被重新加密，或者首先被重新加密 加密，然后转移到第二个位置。 这样可以确保使用第一加密参数或第二加密参数加密的数据总是被移动，从而使攻击者更难以窃听明文数据。

公开(公告)号：US08683217B2

公开(公告)日：2014-03-25

申请号：US11390546

申请日：2006-03-24

申请人： Berndt Gammel ,  Dietmar Scheiblhofer

发明人： Berndt Gammel ,  Dietmar Scheiblhofer

IPC分类号： G06F11/30

CPC分类号： G06F21/85 ,  H04L9/065 ,  H04L2209/12 ,  H04L2209/34

摘要： A device according to the present invention is configured for transmitting data between two semiconductor chips of a data processor in an encrypted manner, wherein a first semiconductor chip is connected to a second semiconductor chip. The device includes a non-volatile memory element in each of the two semiconductor chips, wherein an encryption initial value for an encryption rule is stored in the memory element of the first semiconductor chip and a decryption initial value associated to the encryption initial value for a decryption rule associated to the encryption rule is stored in the memory element of the second semiconductor chip. Additionally, the first semiconductor chip has a first data transmission interface formed to generate an encryption data stream from an input data stream using the encryption initial value according to the encryption rule. Also, the second semiconductor chip has a second data transmission interface formed to receive the encryption data stream and to generate a decryption data stream from the encryption data stream using the decryption initial value according to the decryption rule and to compare the decryption data stream generated to an expected data stream, wherein the second data transmission interface is also formed to perform a defensive measure against transmitting data from the second data transmission interface to the first data transmission interface when the decryption data stream does not correspond to the expected data stream.

摘要翻译： 根据本发明的装置被配置为以加密的方式在数据处理器的两个半导体芯片之间传输数据，其中第一半导体芯片连接到第二半导体芯片。 该装置包括在两个半导体芯片的每一个中的非易失性存储元件，其中用于加密规则的加密初始值存储在第一半导体芯片的存储元件中，以及与加密初始值相关联的解密初始值 与加密规则相关联的解密规则被存储在第二半导体芯片的存储元件中。 此外，第一半导体芯片具有形成为根据加密规则使用加密初始值从输入数据流生成加密数据流的第一数据传输接口。 此外，第二半导体芯片具有形成为接收加密数据流的第二数据传输接口，并且使用根据解密规则的解密初始值从加密数据流生成解密数据流，并将生成的解密数据流与 预期数据流，其中第二数据传输接口还被形成为当解密数据流不对应于期望的数据流时，执行防止措施以将数据从第二数据传输接口传输到第一数据传输接口。