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74 条记录 (耗时 0.043 秒)

    Fault tolerant encoding of directory states for stuck bits
    32.
    发明申请
    Fault tolerant encoding of directory states for stuck bits 有权
    卡位的目录状态的容错编码

    公开(公告)号：US20070079216A1

    公开(公告)日：2007-04-05

    申请号：US11225570

    申请日：2005-09-13

    申请人： Robert Bell ,  Guy Guthrie ,  William Starke

    发明人： Robert Bell ,  Guy Guthrie ,  William Starke

    IPC分类号： G11C29/00

    CPC分类号： G11C29/832 ,  G06F11/1064

    摘要： A method of handling a stuck bit in a directory of a cache memory, by defining multiple binary encodings to indicate a defective cache state, detecting an error in a tag stored in a member of the directory (wherein the tag at least includes an address field, a state field and an error-correction field), determining that the error is associated with a stuck bit of the directory member, and writing new state information to the directory member which is selected from one of the binary encodings based on a field location of the stuck bit within the directory member. The multiple binary encodings may include a first binary encoding when the stuck bit is in the address field, a second binary encoding when the stuck bit is in the state field, and a third binary encoding when the stuck bit is in the error-correction field. The new state information may also further be selected based on the value of the stuck bit, e.g., a state bit corresponding to the stuck bit is assigned a bit value from the new state information which matches the value of the stuck bit.

    摘要翻译： 一种通过定义多个二进制编码来指示缺陷高速缓存状态来处理高速缓冲存储器的目录中的卡住位的方法，检测存储在目录成员中的标签中的错误（其中标签至少包括地址字段 ，状态字段和纠错字段），确定错误与目录成员的卡住位相关联，并且基于字段位置将新状态信息写入从二进制编码之一中选择的目录成员 的目录成员中的卡住位。 多个二进制编码可以包括当卡住位在地址字段中时的第一二进制编码，当卡位位于状态字段时的第二二进制编码，以及当卡位位于错误校正字段中时的第三二进制编码 。 还可以基于卡住位的值进一步选择新的状态信息，例如，对应于该卡住位的状态位从与该卡位的值匹配的新状态信息中分配一位值。

    Cache memory direct intervention
    34.
    发明申请
    Cache memory direct intervention 失效
    缓存内存直接干预

    公开(公告)号：US20060184743A1

    公开(公告)日：2006-08-17

    申请号：US11056673

    申请日：2005-02-12

    申请人： Guy Guthrie ,  William Starke ,  Derek Williams

    发明人： Guy Guthrie ,  William Starke ,  Derek Williams

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0897 ,  G06F12/0831 ,  G06F12/127

    摘要： A method, system, and device for enabling intervention across same-level cache memories. In a preferred embodiment, responsive to a cache miss in a first cache memory a direct intervention request is sent from the first cache memory to a second cache memory requesting a direct intervention that satisfies the cache miss.

    摘要翻译： 一种用于实现跨层级高速缓冲存储器的干预的方法，系统和设备。 在优选实施例中，响应于第一高速缓冲存储器中的高速缓存未命中，直接干预请求从第一高速缓存存储器发送到第二高速缓存存储器，请求满足高速缓存未命中的直接干预。

    Cache member protection with partial make MRU allocation
    36.
    发明申请
    Cache member protection with partial make MRU allocation 失效
    缓存成员保护部分使MRU分配

    公开(公告)号：US20060179234A1

    公开(公告)日：2006-08-10

    申请号：US11054390

    申请日：2005-02-09

    申请人： Robert Bell ,  Guy Guthrie ,  William Starke ,  Jeffrey Stuecheli

    发明人： Robert Bell ,  Guy Guthrie ,  William Starke ,  Jeffrey Stuecheli

    IPC分类号： G06F12/00

    CPC分类号： G06F12/126 ,  G06F12/0897 ,  G06F12/123 ,  G06F12/128

    摘要： A method and apparatus for enabling protection of a particular member of a cache during LRU victim selection. LRU state array includes additional “protection” bits in addition to the state bits. The protection bits serve as a pointer to identify the location of the member of the congruence class that is to be protected. A protected member is not removed from the cache during standard LRU victim selection, unless that member is invalid. The protection bits are pipelined to MRU update logic, where they are used to generate an MRU vector. The particular member identified by the MRU vector (and pointer) is protected from selection as the next LRU victim, unless the member is Invalid. The make MRU operation affects only the lower level LRU state bits arranged a tree-based structure and thus only negates the selection of the protected member, without affecting LRU victim selection of the other members.

    摘要翻译： 一种用于在LRU受害者选择期间能够保护缓存的特定成员的方法和装置。 LRU状态阵列除了状态位之外还包括额外的“保护”位。 保护位用作用于标识要保护的同余类的成员的位置的指针。 在标准LRU受害者选择期间，保护成员不会从缓存中删除，除非该成员无效。 保护位被流水线到MRU更新逻辑，它们用于生成MRU向量。 由MRU向量（和指针）标识的特定成员不被选择作为下一个LRU受害者，除非成员无效。 使MRU操作仅影响布置了基于树的结构的较低级LRU状态位，并且因此仅在不影响其他成员的LRU受害者选择的情况下否定对被保护成员的选择。

    Pipelining D states for MRU steerage during MRU/LRU member allocation
    37.
    发明申请
    Pipelining D states for MRU steerage during MRU/LRU member allocation 失效
    在MRU / LRU成员分配过程中，管理MRU操纵的D状态

    公开(公告)号：US20060179232A1

    公开(公告)日：2006-08-10

    申请号：US11054067

    申请日：2005-02-09

    申请人： Robert Bell ,  Guy Guthrie ,  William Starke ,  Jeffrey Stuecheli

    发明人： Robert Bell ,  Guy Guthrie ,  William Starke ,  Jeffrey Stuecheli

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0888 ,  G06F12/123 ,  G06F12/126 ,  G06F2212/1032

    摘要： A method and apparatus for preventing selection of Deleted (D) members as an LRU victim during LRU victim selection. During each cache access targeting the particular congruence class, the deleted cache line is identified from information in the cache directory. A location of a deleted cache line is pipelined through the cache architecture during LRU victim selection. The information is latched and then passed to MRU vector generation logic. An MRU vector is generated and passed to the MRU update logic, which is selects/tags the deleted member as a MRU member. The make MRU operation affects only the lower level LRU state bits arranged in a tree-based structure state bits so that the make MRU operation only negates selection of the specific member in the D state, without affecting LRU victim selection of the other members.

    摘要翻译： 用于在LRU受害者选择期间防止选择被删除（D）成员作为LRU受害者的方法和装置。 在针对特定同余类的每个缓存访问期间，从高速缓存目录中的信息识别已删除的高速缓存行。 删除的高速缓存行的位置在LRU受害者选择期间通过高速缓存架构流水线化。 信息被锁存，然后传递给MRU向量生成逻辑。 生成MRU向量并将其传递给MRU更新逻辑，MRU更新逻辑是将删除的成员作为MRU成员进行选择/标记。 使MRU操作仅影响以基于树的结构状态位布置的较低级LRU状态位，使得MRU操作仅在D状态下否定特定成员的选择，而不影响其他成员的LRU受害者选择。

    Data Processing System and Method for Efficient L3 Cache Directory Management
    39.
    发明申请
    Data Processing System and Method for Efficient L3 Cache Directory Management 有权
    数据处理系统和高效L3缓存目录管理方法

    公开(公告)号：US20080098177A1

    公开(公告)日：2008-04-24

    申请号：US11956112

    申请日：2007-12-13

    申请人： Guy Guthrie ,  William Starke ,  Derek Williams ,  Philip Williams

    发明人： Guy Guthrie ,  William Starke ,  Derek Williams ,  Philip Williams

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0811 ,  G06F12/0831 ,  G06F12/128 ,  G06F2212/2542

    摘要： A system and method for cache management in a data processing system having a memory hierarchy of upper memory and lower memory cache. A lower memory cache controller accesses a coherency state table to determine replacement policies of coherency states for cache lines present in the lower memory cache when receiving a cast-in request from one of the upper memory caches. The coherency state table implements a replacement policy that retains the more valuable cache coherency state information between the upper and lower memory caches for a particular cache line contained in both levels of memory at the time of cast-out from the upper memory cache.

    摘要翻译： 一种用于在具有上部存储器和下部存储器高速缓存的存储器层级的数据处理系统中的高速缓存管理的系统和方法。 较低的存储器高速缓存控制器访问一致性状态表以确定当从上部存储器高速缓存中的一个接收到转入请求时存在于下部存储器高速缓存中的高速缓存行的一致性状态的替换策略。 一致性状态表实现替换策略，其在从上部存储器高速缓存中拔出时，在包含在两个级别的存储器中的特定高速缓存行的上下存储器高速缓存之间保留更有价值的高速缓存一致性状态信息。

    Reducing Number of Rejected Snoop Requests By Extending Time To Respond To Snoop Request
    40.
    发明申请
    Reducing Number of Rejected Snoop Requests By Extending Time To Respond To Snoop Request 失效
    通过延长响应Snoop请求的时间减少被拒绝的侦听请求数

    公开(公告)号：US20080077744A1

    公开(公告)日：2008-03-27

    申请号：US11950717

    申请日：2007-12-05

    申请人： Benjiman Goodman ,  Guy Guthrie ,  William Starke ,  Jeffrey Stuecheli ,  Derek Williams

    发明人： Benjiman Goodman ,  Guy Guthrie ,  William Starke ,  Jeffrey Stuecheli ,  Derek Williams

    IPC分类号： G06F13/28

    CPC分类号： G06F12/0831

    摘要： A cache, system and method for reducing the number of rejected snoop requests. A “stall/reorder unit” in a cache receives a snoop request from an interconnect. Information, such as the address, of the snoop request is stored in a queue of the stall/reorder unit. The stall/reorder unit forwards the snoop request to a selector which also receives a request from a processor. An arbitration mechanism selects either the snoop request or the request from the processor. If the snoop request is denied by the arbitration mechanism, information, e.g., address, about the snoop request may be maintained in the stall/reorder unit. The request may be later resent to the selector. This process may be repeated up to “n” clock cycles. By providing the snoop request additional opportunities (n clock cycles) to be accepted by the arbitration mechanism, fewer snoop requests may ultimately be denied.

    摘要翻译： 用于减少拒绝的窥探请求数量的缓存，系统和方法。 缓存中的“停止/重新排序单元”从互连中接收窥探请求。 窥探请求的诸如地址的信息被存储在失速/重新排序单元的队列中。 停止/重新排序单元将窥探请求转发到也从处理器接收请求的选择器。 仲裁机制选择来自处理器的窥探请求或请求。 如果侦听请求被仲裁机制拒绝，关于窥探请求的信息（例如地址）可以被保留在停止/重新排序单元中。 请求可能会稍后重新发送到选择器。 该过程可以重复直到“n”个时钟周期。 通过提供窥探请求仲裁机制接受的额外机会（n个时钟周期），最终可能会拒绝更少的侦听请求。