Data Processing System and Method for Efficient L3 Cache Directory Management
    2.
    发明申请
    Data Processing System and Method for Efficient L3 Cache Directory Management 有权
    数据处理系统和高效L3缓存目录管理方法

    公开(公告)号:US20080098177A1

    公开(公告)日:2008-04-24

    申请号:US11956112

    申请日:2007-12-13

    IPC分类号: G06F12/00

    摘要: A system and method for cache management in a data processing system having a memory hierarchy of upper memory and lower memory cache. A lower memory cache controller accesses a coherency state table to determine replacement policies of coherency states for cache lines present in the lower memory cache when receiving a cast-in request from one of the upper memory caches. The coherency state table implements a replacement policy that retains the more valuable cache coherency state information between the upper and lower memory caches for a particular cache line contained in both levels of memory at the time of cast-out from the upper memory cache.

    摘要翻译: 一种用于在具有上部存储器和下部存储器高速缓存的存储器层级的数据处理系统中的高速缓存管理的系统和方法。 较低的存储器高速缓存控制器访问一致性状态表以确定当从上部存储器高速缓存中的一个接收到转入请求时存在于下部存储器高速缓存中的高速缓存行的一致性状态的替换策略。 一致性状态表实现替换策略,其在从上部存储器高速缓存中拔出时,在包含在两个级别的存储器中的特定高速缓存行的上下存储器高速缓存之间保留更有价值的高速缓存一致性状态信息。

    Data processing system, cache system and method for scrubbing a domain indication in response to execution of program code
    4.
    发明申请
    Data processing system, cache system and method for scrubbing a domain indication in response to execution of program code 有权
    数据处理系统,缓存系统和用于响应于程序代码的执行来擦除域指示的方法

    公开(公告)号:US20060271741A1

    公开(公告)日:2006-11-30

    申请号:US11136642

    申请日:2005-05-24

    IPC分类号: G06F13/28

    CPC分类号: G06F12/0831 G06F12/0813

    摘要: In response to execution of program code, a control register within scrubbing logic in a local coherency domain is initialized with at least a target address of a target memory block. In response to the initialization, the scrubbing logic issues to at least one cache hierarchy in a remote coherency domain a domain indication scrubbing request targeting a target memory block that may be cached by the at least one cache hierarchy. In response to receipt of a coherency response indicating that the target memory block is not cached in the remote coherency domain, a domain indication in the local coherency domain is updated to indicate that the target memory block is cached, if at all, only within the local coherency domain.

    摘要翻译: 响应于程序代码的执行,用至少目标存储器块的目标地址初始化局部一致性域内的擦除逻辑中的控制寄存器。 响应于初始化,擦除逻辑向远程一致性域中的至少一个高速缓存层级发出针对可由所述至少一个高速缓存层级缓存的目标存储器块的域指示擦除请求。 响应于接收到指示目标存储器块未被缓存在远程一致性域中的一致性响应,本地一致性域中的域指示被更新以指示目标存储器块被缓存,如果完全只在 局部一致性域。

    Reducing number of rejected snoop requests by extending time to respond to snoop request

    公开(公告)号:US20060184749A1

    公开(公告)日:2006-08-17

    申请号:US11056764

    申请日:2005-02-11

    IPC分类号: G06F13/28

    CPC分类号: G06F12/0831

    摘要: A cache, system and method for reducing the number of rejected snoop requests. An incoming snoop request is entered in the first available latch in a pipeline of latches in a stall/reorder unit if the stall/reorder unit is not full. The entered snoop request is dispatched to a selector upon entering a bottom latch in the pipeline. The stall/reorder unit is not informed as to whether the dispatched snoop request is accepted by an arbitration mechanism for several clock cycles after the dispatch occurred. A copy of the dispatched snoop request is stored in a top latch in an overrun pipeline of latches in the first unit upon dispatching the snoop request. By maintaining information about the snoop request, the snoop request may be dispatched again to the selector in case the dispatched snoop request was rejected thereby increasing the chance that the snoop request will ultimately be accepted.

    Processor, data processing system and method for synchronzing access to data in shared memory
    6.
    发明申请
    Processor, data processing system and method for synchronzing access to data in shared memory 有权
    处理器,数据处理系统和方法,用于同步共享存储器中数据的访问

    公开(公告)号:US20060085603A1

    公开(公告)日:2006-04-20

    申请号:US10965113

    申请日:2004-10-14

    IPC分类号: G06F12/00

    摘要: A processing unit for a multiprocessor data processing system includes a store-through upper level cache, an instruction sequencing unit that fetches instructions for execution, at least one instruction execution unit that executes a store-conditional instruction to determine a store target address, a store queue that, following execution of the store-conditional instruction, buffers a corresponding store operation, sequencer logic associated with the store queue. The sequencer logic, responsive to receipt of a latency indication indicating that resolution of the store-conditional operation as passing or failing is subject to significant latency, invalidates, prior to resolution of the store-conditional operation, a cache line in the store-through upper level cache to which a load-reserve operation previously bound.

    摘要翻译: 一种用于多处理器数据处理系统的处理单元,包括存储器上级缓存器,取指令执行指令排序单元,执行存储条件指令以确定存储目标地址的至少一个指令执行单元,存储器 在存储条件指令的执行之后,缓存与存储队列相关联的对应存储操作,定序器逻辑的队列。 定序器逻辑响应于指示存储条件操作的解析作为传递或失败的等待时间指示受到重大等待时间的影响,在存储条件操作的解析之前无效,存储器中的高速缓存行 加载预备操作先前绑定到的高级缓存。

    Data processing system, cache system and method for precisely forming an invalid coherency state indicating a broadcast scope
    7.
    发明申请
    Data processing system, cache system and method for precisely forming an invalid coherency state indicating a broadcast scope 失效
    数据处理系统,缓存系统和精确形成指示广播范围的无效一致性状态的方法

    公开(公告)号:US20070168618A1

    公开(公告)日:2007-07-19

    申请号:US11333615

    申请日:2006-01-17

    IPC分类号: G06F13/28

    CPC分类号: G06F12/0831

    摘要: A cache coherent data processing system includes at least first and second coherency domains. In a first cache memory within the first coherency domain of the data processing system, a memory block is held in a storage location associated with an address tag and a coherency state field. A determination is made if a home system memory assigned an address associated with the memory block is within the first coherency domain. If not, the coherency state field is set to a coherency state that indicates that the address tag is valid, that the storage location does not contain valid data, the first coherency domain does not contain the home system memory, and that, following formation of the coherency state, the memory block is cached outside of the first coherency domain.

    摘要翻译: 缓存相干数据处理系统至少包括第一和第二相干域。 在数据处理系统的第一相关域内的第一高速缓存存储器中,存储块被保存在与地址标签和一致性状态字段相关联的存储位置中。 如果分配了与存储器块相关联的地址的归属系统存储器在第一相干域内,则确定。 如果不是,则将一致性状态字段设置为指示地址标签有效的一致性状态,即存储位置不包含有效数据,第一相干域不包含家庭系统存储器,并且在形成 一致性状态下,内存块被缓存在第一个相干域之外。

    Reducing number of rejected snoop requests by extending time to respond to snoop request

    公开(公告)号:US20060184748A1

    公开(公告)日:2006-08-17

    申请号:US11056740

    申请日:2005-02-11

    IPC分类号: G06F13/28

    CPC分类号: G06F12/0831

    摘要: A cache, system and method for reducing the number of rejected snoop requests. A “stall/reorder unit” in a cache receives a snoop request from an interconnect. Information, such as the address, of the snoop request is stored in a queue of the stall/reorder unit. The stall/reorder unit forwards the snoop request to a selector which also receives a request from a processor. An arbitration mechanism selects either the snoop request or the request from the processor. If the snoop request is denied by the arbitration mechanism, information, e.g., address, about the snoop request may be maintained in the stall/reorder unit. The request may be later resent to the selector. This process may be repeated up to “n” clock cycles. By providing the snoop request additional opportunities (n clock cycles) to be accepted by the arbitration mechanism, fewer snoop requests may ultimately be denied.