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31.发明授权Address dependent caching behavior within a data processing system having HSA (hashed storage architecture) 失效具有HSA（散列存储架构）的数据处理系统中的依赖于地址的缓存行为公开(公告)号：US06446165B1
公开(公告)日：2002-09-03
申请号：US09364287
申请日：1999-07-30
IPC分类号： G06F1300
CPC分类号： G06F12/0811
摘要： A processor includes at least one execution unit, an instruction sequencing unit coupled to the execution unit, and a plurality of caches at a same level. The caches, which store data utilized by the execution unit, each store only data having associated addresses within a respective one of a plurality of subsets of an address space and implement diverse caching behaviors. The diverse caching behaviors can include differing memory update policies, differing coherence protocols, differing prefetch behaviors, and differing cache line replacement policies.
摘要翻译： 处理器包括至少一个执行单元，耦合到执行单元的指令排序单元和在同一级别的多个高速缓存。 存储由执行单元使用的数据的高速缓存仅存储具有地址空间的多个子集中的相应地址内的相关联地址的数据，并且实现多种缓存行为。 不同的缓存行为可以包括不同的内存更新策略，不同的一致性协议，不同的预取行为以及不同的缓存行替换策略。
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32.发明授权Multiprocessor system bus with system controller explicitly updating snooper LRU information 失效具有系统控制器的多处理器系统总线显式更新窥探LRU信息公开(公告)号：US06338124B1
公开(公告)日：2002-01-08
申请号：US09368229
申请日：1999-08-04
IPC分类号： G06F1208
CPC分类号： G06F12/123 , G06F12/0831
摘要： Combined response logic for a bus receives a combined data access and cast out/deallocate operation initiating by a storage device within a specific level of a storage hierarchy, with a coherency state and LRU position of the cast out/deallocate victim appended. Snoopers on the bus drive snoop responses to the combined operation with the coherency state and/or LRU position of locally-stored cache lines corresponding to the victim appended. The combined response logic determines, from the coherency state and LRU position information appended to the combined operation and the snoop responses, whether an update of the LRU position and/or coherency state of a cache line corresponding to the victim within one of the snoopers is required. If so, the combined response logic selects a snooper storage device to have at least the LRU position of a respective cache line corresponding to the victim updated, and appends an update command identifying the selected snooper to the combined response. The snooper selected to be updated may be randomly chosen, selected based on LRU position of the cache line corresponding to the victim within respective storage, or selected based on other criteria.
摘要翻译： 总线的组合响应逻辑接收组合的数据访问，并且通过由存储层级的特定级别中的存储设备发起/撤销分配操作，附加了外推/解除分配的受害者的一致性状态和LRU位置。 总线驱动器侦听器上的侦听器响应于与所附加的受害者对应的本地存储的缓存线的相关性状态和/或LRU位置的组合操作。 组合响应逻辑从相关性状态和附加到组合操作和窥探响应的LRU位置信息中确定与窥探者之一内的受害者对应的高速缓存线的LRU位置和/或一致性状态的更新是否是 需要。 如果是，组合的响应逻辑选择窥探存储设备至少具有与受害者相对应的相应高速缓存行的LRU位置更新，并且将识别所选窥探者的更新命令附加到组合响应。 选择要更新的窥探者可以被随机地选择，基于在相应存储器内对应于受害者的高速缓存线的LRU位置来选择，或者基于其他标准来选择。
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33.发明授权Multiprocessor system bus with combined snoop responses explicitly cancelling master allocation of read data 失效具有组合侦听响应的多处理器系统总线显式地取消读取数据的主分配公开(公告)号：US06321305B1
公开(公告)日：2001-11-20
申请号：US09368230
申请日：1999-08-04
IPC分类号： G06F1200
CPC分类号： G06F12/0804 , G06F12/0811 , G06F12/0888
摘要： In cancelling the cast out portion of a combined operation including a data access related to the cast out, the combined response logic explicitly directs the storage device initiating the combined operation not to allocate storage for the target of the data access. Instead, the target of the data access may be passed directly to an in-line processor core without storage, may be stored in a horizontal storage device, or may be stored in an in-line, noninclusive, lower level storage device. Cancellation of the cast out thus defers any latency associated with writing the cast out victim to system memory while maximizing utilization of available storage with acceptable tradeoffs in data access latency.
摘要翻译： 组合响应逻辑在取消组合操作包括与丢弃相关的数据访问的部署时，明确地指示存储设备启动组合操作，而不为数据访问的目标分配存储。 相反，数据访问的目标可以直接传递到没有存储的在线处理器核心，可以被存储在水平存储设备中，或者可以被存储在一个在线的，独立的，低级的存储设备中。 取消投票，从而延迟与将丢弃的受害者写入系统内存相关的任何延迟，同时最大限度地利用可用存储在数据访问延迟中具有可接受的折中。
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34.发明授权Data processing system having demand based write through cache with enforced ordering 失效数据处理系统具有基于需求的写入通过缓存执行排序
公开(公告)号：US5796979A
公开(公告)日：1998-08-18
申请号：US730994
申请日：1996-10-16
CPC分类号： G06F12/0866 , G06F12/0815 , G06F12/0835 , G06F2212/303
摘要： A data processing system includes a processor, a system memory, one or more input/output channel controllers (IOCC), and a system bus connecting the processor, the memory and the IOCCs together for communicating instructions, address and data between the various elements of a system. The IOCC includes a paged cache storage having a number of lines wherein each line of the page may be, for example, 32 bytes. Each page in the cache also has several attribute bits for that page including the so called WIM and attribute bits. The W bit is for controlling write through operations; the I bit controls cache inhibit; and the M bit controls memory coherency. Since the IOCC is unaware of these page table attribute bits for the cache lines being DMAed to system memory, IOCC must maintain memory consistency and cache coherency without sacrificing performance. For DMA write data to system memory, new cache attributes called global, cachable and demand based write through are created. Individual writes within a cache line are gathered by the IOCC and only written to system memory when the I/O bus master accesses a different cache line or relinquishes the I/O bus.
摘要翻译： 数据处理系统包括处理器，系统存储器，一个或多个输入/输出通道控制器（IOCC）以及将处理器，存储器和IOCC连接在一起的系统总线，用于在各种元件之间传送指令，地址和数据 一个系统。 IOCC包括具有多行的分页缓存存储器，其中页面的每行可以是例如32字节。 缓存中的每个页面还具有该页面的几个属性位，包括所谓的WIM和属性位。 W位用于控制写操作; I位控制缓存抑制; M位控制存储器一致性。 由于IOCC不知道将这些页表属性位用于高速缓存行被DMA映射到系统内存，因此IOCC必须保持内存一致性和高速缓存一致性，而不会牺牲性能。 对于将DMA写入数据到系统内存，创建了称为全局，可高速缓存和基于需求的写入的新缓存属性。 高速缓存行中的单独写入由IOCC收集，只有当I / O总线主机访问不同的高速缓存行或放弃I / O总线时才写入系统存储器。
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35.发明授权Hashing a target address for a memory access instruction in order to determine prior to execution which particular load/store unit processes the instruction 失效为存储器访问指令散列目标地址，以便在执行之前确定哪个特定的加载/存储单元处理该指令公开(公告)号：US06658556B1
公开(公告)日：2003-12-02
申请号：US09364288
申请日：1999-07-30
IPC分类号： G06F1730
CPC分类号： G06F9/3885 , G06F9/3013 , G06F9/3802 , G06F9/3814 , G06F9/3824 , G06F9/384 , G06F9/3891
摘要： A processor includes execution resources, data storage, and an instruction sequencing unit, coupled to the data storage and the execution resources, that supplies instructions within the data storage to the execution resources. The execution resources include a plurality of load-store units that each process only instructions that access data having associated addresses within a respective one of a plurality of subsets of an address space. The load-store units can have diverse hardware such that a maximum number of instructions that can be concurrently executed is different for different load-store units or such that some of the load-store units are restricted to executing certain classes of instructions.
摘要翻译： 处理器包括执行资源，数据存储和与数据存储器和执行资源耦合的指令排序单元，其将数据存储器内的指令提供给执行资源。 执行资源包括多个加载存储单元，每个加载存储单元仅处理在地址空间的多个子集中的相应一个子集内访问具有相关联地址的数据的指令。 加载存储单元可以具有不同的硬件，使得可以并发执行的最大数量的指令对于不同的加载存储单元是不同的，或者使得一些加载存储单元被限制为执行某些类别的指令。
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36.发明授权Multiprocessor system bus with combined snoop responses explicitly informing snoopers to scarf data 失效具有组合侦听响应的多处理器系统总线显式通知窥探者围绕数据公开(公告)号：US06502171B1
公开(公告)日：2002-12-31
申请号：US09368231
申请日：1999-08-04
IPC分类号： G06F1200
CPC分类号： G06F12/0831 , G06F12/0811
摘要： In cancelling the cast out portion of a combined operation including a data access related to the cast out, the combined response logic explicitly directs a horizontal storage device at the same level as the storage device initiating the combined operation to allocate and store either the cast out or target data. A horizontal storage device having available space—i.e., an invalid or modified data element in a congruence class for the victim—stores either the target or the cast out data for subsequent access by an intervention. Cancellation of the cast out thus defers any latency associated with writing the cast out victim to system memory while maximizing utilization of available storage with acceptable tradeoffs in data access latency.
摘要翻译： 组合响应逻辑在取消组合操作包括与丢弃相关的数据访问的组合操作时，明确指示与启动组合操作的存储设备处于同一级别的水平存储设备，以分配和存储任务 或目标数据。 具有可用空间的水平存储设备（即，用于受害者的同余类中的无效或修改的数据元素）存储目标或丢弃数据以供随后的干预访问。 取消投票，从而延迟与将丢弃的受害者写入系统内存相关的任何延迟，同时最大限度地利用可用存储在数据访问延迟中具有可接受的折中。
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公开(公告)号：US06449691B1
公开(公告)日：2002-09-10
申请号：US09364285
申请日：1999-07-30
IPC分类号： G06F1300
CPC分类号： G06F12/0846 , G06F12/0607 , G06F12/0848 , G06F12/0864 , G06F12/0897
摘要： A processor includes at least one execution unit, an instruction sequencing unit coupled to the execution unit, and a plurality of caches at a same level. The caches, which store data utilized by the execution unit, have diverse cache hardware and each preferably store only data having associated addresses within a respective one of a plurality of subsets of an address space. The diverse cache hardware can include, for example, differing cache sizes, differing associativities, differing sectoring, and differing inclusivities.
摘要翻译： 处理器包括至少一个执行单元，耦合到执行单元的指令排序单元和在同一级别的多个高速缓存。 存储由执行单元使用的数据的高速缓存具有不同的高速缓存硬件，并且每个高速缓存优选仅存储具有地址空间的多个子集中的相应地址内的相关联的地址的数据。 不同的高速缓存硬件可以包括例如不同的高速缓存大小，不同的相关性，不同的扇区和不同的包容性。
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38.发明授权公开(公告)号：US06516404B1
公开(公告)日：2003-02-04
申请号：US09364283
申请日：1999-07-30
IPC分类号： G06F1200
CPC分类号： G06F9/3012 , G06F9/3013 , G06F9/30138 , G06F9/3016 , G06F9/384 , G06F12/06 , G06F12/0846
摘要： A processor having a hashed and partitioned register file includes at least one execution unit, an instruction sequencing unit coupled to the execution unit, and a plurality of registers coupled to the execution unit. The plurality of registers are partitioned into a plurality of groups, such that registers within each group can store only data having associated addresses within a respective one of a plurality of subsets of an address space.
摘要翻译： 具有散列和分区寄存器文件的处理器包括至少一个执行单元，耦合到执行单元的指令排序单元和耦合到执行单元的多个寄存器。 多个寄存器被划分成多个组，使得每个组中的寄存器可以仅存储具有地址空间的多个子集中的相应地址内的相关联地址的数据。
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39.发明授权Method and system for communication in which a castout operation is cancelled in response to snoop responses 失效用于通信的方法和系统，其中响应于窥探响应取消了退出操作公开(公告)号：US06349367B1
公开(公告)日：2002-02-19
申请号：US09368228
申请日：1999-08-04
IPC分类号： G06F1300
CPC分类号： G06F12/0831 , G06F12/0804
摘要： An effectively “conditional”, cast out operation or cast out portion of a combined operation including a related data access may be cancelled by the combined response to the operation. The combined response logic receives coherency state and/or LRU position information for cache lines corresponding to the cast out victim within snoopers and vertically in-line storage. The combined response logic may also receive information regarding the presence of shared or invalid cache lines in snoopers or lower level storage within the congruence class for the victim, or information regarding the read-once nature of the data access target. Based on these responses, the combined response logic determines whether the cast out should be cancelled and, if so, selects and drives the appropriate combined response code.
摘要翻译： 可以通过对操作的组合的响应来取消有效的“有条件”，丢弃包括相关数据访问在内的组合操作的部分。 组合的响应逻辑在窥探者和垂直的在线存储器中接收对应于被丢弃的受害者的高速缓存行的相关性状态和/或LRU位置信息。 组合的响应逻辑还可以接收关于在受害者的同余类中的窥探者或低级存储器中存在共享或无效高速缓存行的信息，或者关于数据访问目标的一次读取性质的信息。 基于这些响应，组合的响应逻辑确定是否应该取消推出，如果是，则选择并驱动适当的组合响应代码。
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40.发明授权Multiprocessor system bus with combined snoop responses implicitly updating snooper LRU position 失效具有组合侦听响应的多处理器系统总线隐式更新snooper LRU位置公开(公告)号：US06279086B1
公开(公告)日：2001-08-21
申请号：US09368227
申请日：1999-08-04
IPC分类号： G06F1208
CPC分类号： G06F12/0811 , G06F12/0831 , G06F12/123
摘要： Upon snooping a combined data access and cast out/deallocate operation initiating by a horizontal storage device, snoop logic determines, from LRU position information appended to the combined response to the combined operation, whether the coherency state and/or LRU position of the victim may be upgraded within the subject storage device. If so, the coherency state or LRU position is upgraded to improve global data storage management. For instance, a cache line within a snooping storage device may be altered to assume the coherency state of the victim within the storage device initiating the combined operation to improve data storage management under a given replacement policy.
摘要翻译： 在窥探组合的数据访问并且通过水平存储设备推出/取消分配操作时，窥探逻辑从附加到对组合操作的组合响应的LRU位置信息确定受害者的相关性状态和/或LRU位置是否可以 在主题存储设备内进行升级。 如果是这样，则一致性状态或LRU位置被升级以改进全局数据存储管理。 例如，可以改变窥探存储设备内的高速缓存行，以假定存储设备内的受害者的一致性状态发起组合操作，以改善给定替换策略下的数据存储管理。
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