公开(公告)号：US20110320694A1

公开(公告)日：2011-12-29

申请号：US12821721

申请日：2010-06-23

申请人： Deanna Postles Dunn Berger ,  Michael F. Fee ,  Robert J. Sonnelitter, III

发明人： Deanna Postles Dunn Berger ,  Michael F. Fee ,  Robert J. Sonnelitter, III

IPC分类号： G06F12/08 ,  G06F12/02

CPC分类号： G06F12/0857 ,  G06F12/084

摘要： A method of performing operations in a shared cache coupled to a first requestor and a second requestor includes receiving at the shared cache a first request from the second requester; assigning the request to a state machine; transmitting a first pipe pass request from the state machine to an arbiter; providing a first instruction from the first pipe pass request to a cache pipeline, the first instruction causing a first pipe pass; and providing a second pipe pass request to the arbiter before the first pipe pass is completed.

摘要翻译： 一种在耦合到第一请求者和第二请求者的共享高速缓存中执行操作的方法包括：在所述共享缓存处接收来自所述第二请求者的第一请求; 将请求分配给状态机; 将来自状态机的第一管道通过请求发送到仲裁器; 提供从所述第一管道通过请求到高速缓存流水线的第一指令，所述第一指令引起第一管道通过; 以及在第一管道通过完成之前向仲裁者提供第二管道通过请求。

公开(公告)号：US20110320659A1

公开(公告)日：2011-12-29

申请号：US12821739

申请日：2010-06-23

申请人： Ekaterina M. Ambroladze ,  Deanna Postles Dunn Berger ,  Diana Lynn Orf ,  Robert J. Sonnelitter, III

发明人： Ekaterina M. Ambroladze ,  Deanna Postles Dunn Berger ,  Diana Lynn Orf ,  Robert J. Sonnelitter, III

IPC分类号： G06F13/00 ,  G06F13/18 ,  G06F12/08

CPC分类号： G06F13/1642 ,  G06F12/0811 ,  G06F12/084

摘要： An apparatus for controlling access to a resource includes a shared pipeline configured to communicate with the resource, a plurality of command queues configured to form instructions for the shared pipeline and an arbiter coupled between the shared pipeline and the plurality of command queues configured to grant access to the shared pipeline to a one of the plurality of command queues based on a first priority scheme in a first operating mode. The apparatus also includes interface logic coupled to the arbiter and configured to determine that contention for access to the resource exists among the plurality of command queues and to cause the arbiter to grant access to the shared pipeline based on a second priority scheme in second operating mode.

摘要翻译： 用于控制对资源的访问的装置包括被配置为与资源通信的共享流水线，多个命令队列，被配置为形成用于共享流水线的指令，以及耦合在共享流水线与被配置为授权访问的多个命令队列之间的仲裁器 基于第一操作模式中的第一优先级方案将所述共享流水线传送到所述多个命令队列中的一个。 该装置还包括耦合到仲裁器并被配置为确定在多个命令队列中存在对资源的访问的竞争的接口逻辑，并且使得仲裁器基于第二操作模式中的第二优先级方案来允许对共享流水线的访问 。

公开(公告)号：US08006039B2

公开(公告)日：2011-08-23

申请号：US12036322

申请日：2008-02-25

申请人： Deanna P. Dunn ,  Robert J. Sonnelitter, III ,  Gary E. Strait

发明人： Deanna P. Dunn ,  Robert J. Sonnelitter, III ,  Gary E. Strait

IPC分类号： G06F13/00

CPC分类号： G06F13/28 ,  G06F12/0866

摘要： A method for merging data including receiving a request from an input/output device to merge a data, wherein a merge of the data includes a manipulation of the data, determining if the data exists in a local cache memory that is in local communication with the input/output device, fetching the data to the local cache memory from a remote cache memory or a main memory if the data does not exist in the local cache memory, merging the data according to the request to obtain a merged data, and storing the merged data in the local cache, wherein the merging of the data is performed without using a memory controller within a control flow or a data flow of the merging of the data. A corresponding system and computer program product.

摘要翻译： 一种用于合并数据的方法，包括接收来自输入/输出设备的请求以合并数据，其中所述数据的合并包括对所述数据的操纵，确定所述数据是否存在于与所述数据本地通信的本地高速缓冲存储器中 输入/输出设备，如果数据不存在于本地高速缓冲存储器中，则从远程高速缓冲存储器或主存储器将数据提取到本地高速缓冲存储器，根据请求合并数据以获得合并数据，并存储 合并的数据在本地高速缓存中，其中在不使用控制流中的存储器控​​制器或合并数据的数据流的情况下执行数据的合并。 相应的系统和计算机程序产品。

公开(公告)号：US20090006693A1

公开(公告)日：2009-01-01

申请号：US11768934

申请日：2007-06-27

申请人： Deanna P. Dunn ,  Christine C. Jones ,  Arthur J. O'Neill ,  Vesselina K. Papazova ,  Robert J. Sonnelitter, III ,  Craig R. Walters

发明人： Deanna P. Dunn ,  Christine C. Jones ,  Arthur J. O'Neill ,  Vesselina K. Papazova ,  Robert J. Sonnelitter, III ,  Craig R. Walters

IPC分类号： G06F13/14

CPC分类号： G06F13/14 ,  G06F9/50 ,  G06F2209/5021 ,  Y02D10/14 ,  Y02D10/22

摘要： A modification of rank priority arbitration for access to computer system resources through a shared pipeline that provides more equitable arbitration by allowing a higher ranked request access to the shared resource ahead of a lower ranked requester only one time. If multiple requests are active at the same time, the rank priority will first select the highest priority active request and grant it access to the resource. It will also set a ‘blocking latch’ to prevent that higher priority request from re-gaining access to the resource until the rest of the outstanding lower priority active requesters have had a chance to access the resource.

摘要翻译： 通过共享流水线访问计算机系统资源的等级优先仲裁的修改，通过允许较高排名的请求仅在较低等级的请求者之前访问共享资源，提供更公平的仲裁。 如果多个请求同时处于活动状态，则排名优先级将首先选择最高优先级的活动请求并授予对资源的访问权限。 它还将设置一个“阻塞锁定”，以防止更高优先级的请求重新获得对资源的访问，直到其余的优先级较低的主动请求者有机会访问该资源。

公开(公告)号：US08560803B2

公开(公告)日：2013-10-15

申请号：US12821714

申请日：2010-06-23

申请人： Diana L. Orf ,  Robert J. Sonnelitter, III

发明人： Diana L. Orf ,  Robert J. Sonnelitter, III

IPC分类号： G06F12/08

CPC分类号： G06F12/0811 ,  G06F12/084

摘要： An apparatus for controlling operation of a cache includes a first command queue, a second command queue and an input controller configured to receive requests having a first command type and a second command type and to assign a first request having the first command type to the first command queue and a second command having the first command type to the second command queue in the event that the first command queue has not received an indication that a first dedicated buffer is available.

摘要翻译： 一种用于控制高速缓存操作的装置包括：第一命令队列，第二命令队列和输入控制器，被配置为接收具有第一命令类型和第二命令类型的请求，并将具有第一命令类型的第一请求分配给第一命令类型 在第一命令队列尚未接收到第一专用缓冲器可用的指示的情况下，具有第一命令类型的命令队列和第二命令到第二命令队列。

公开(公告)号：US08539158B2

公开(公告)日：2013-09-17

申请号：US13173840

申请日：2011-06-30

申请人： Deanna Postles Dunn ,  Robert J. Sonnelitter, III ,  Gary E. Strait

发明人： Deanna Postles Dunn ,  Robert J. Sonnelitter, III ,  Gary E. Strait

IPC分类号： G06F12/08

CPC分类号： G06F13/28 ,  G06F12/0866

摘要： A method for merging data including receiving a request from an input/output device to merge a data, wherein a merge of the data includes a manipulation of the data, determining that the data exists in a local cache memory that is in local communication with the input/output device, fetching the data to the local cache memory from a remote cache memory or a main memory if the data does not exist in the local cache memory, merging the data according to the request to obtain a merged data, and storing the merged data in the local cache, wherein the merging of the data is performed without using a memory controller within a control flow or a data flow of the merging of the data.

摘要翻译： 一种用于合并数据的方法，包括接收来自输入/输出设备的请求以合并数据，其中所述数据的合并包括所述数据的操作，确定所述数据存在于与所述数据本地通信的本地高速缓冲存储器中 输入/输出设备，如果数据不存在于本地高速缓冲存储器中，则从远程高速缓冲存储器或主存储器将数据提取到本地高速缓冲存储器，根据请求合并数据以获得合并数据，并存储 合并的数据在本地高速缓存中，其中在不使用控制流中的存储器控​​制器或合并数据的数据流的情况下执行数据的合并。

公开(公告)号：US08495287B2

公开(公告)日：2013-07-23

申请号：US12822882

申请日：2010-06-24

申请人： Adam B. Collura ,  Michael Fee ,  Arthur J. O'Neill, Jr. ,  Gerard M. Salem ,  Robert J. Sonnelitter, III

发明人： Adam B. Collura ,  Michael Fee ,  Arthur J. O'Neill, Jr. ,  Gerard M. Salem ,  Robert J. Sonnelitter, III

IPC分类号： G06F12/08 ,  G06F12/16

CPC分类号： G06F11/073 ,  G06F11/0751

摘要： A method of debugging an embedded dynamic random access memory (eDRAM) element of a processor core is provided. An aspect includes, based on an error occurring in the eDRAM element, stopping a functional clock, and not stopping a refresh clock. Another aspect includes, based on the functional clock being stopped, creating a fence signal that prevents all commands other than a refresh command, the refresh command being based on the refresh clock, from entering into the eDRAM element. Another aspect includes initializing a line fetch controller of the processor core with at least one of write data and read data. Another aspect includes restarting the functional clock. Another aspect includes performing at least one of write requests and read requests to the eDRAM element based on the at least one of the write data and the read data from the line fetch controller based on the functional clock.

摘要翻译： 提供了一种调试处理器核心的嵌入式动态随机存取存储器（eDRAM）元件的方法。 一个方面包括基于eDRAM元件中发生的错误，停止功能时钟，而不是停止刷新时钟。 另一方面包括基于停止的功能时钟，创建围栏信号，该屏障信号防止刷新命令以外的所有命令（刷新命令基于刷新时钟）进入eDRAM元素。 另一方面包括用写入数据和读取数据中的至少一个初始化处理器核心的线取指控制器。 另一方面包括重启功能时钟。 另一方面包括基于功能时钟，基于来自线取指控制器的写入数据和读取数据中的至少一个，向eDRAM元件执行至少一个写入请求和读取请求。

公开(公告)号：US08478920B2

公开(公告)日：2013-07-02

申请号：US12822333

申请日：2010-06-24

申请人： Garrett M. Drapala ,  Kenneth D. Klapproth ,  Robert J. Sonnelitter, III ,  Craig R. Walters

发明人： Garrett M. Drapala ,  Kenneth D. Klapproth ,  Robert J. Sonnelitter, III ,  Craig R. Walters

IPC分类号： G06F13/00

CPC分类号： G06F13/26

摘要： A mechanism for controlling data stream interruptions on a shared bus is provided. A first request is received to transfer data. High priority data components and low priority data components are determined for the first request. The high priority data components are transferred without interruptions. In response to receiving requests when transferring the high priority data components, the received requests are rejected.

摘要翻译： 提供了一种用于控制共享总线上的数据流中断的机制。 接收到第一个要求来传输数据。 为第一个请求确定高优先级数据组件和低优先级数据组件。 高优先级数据组件无间断地传输。 响应于在传送高优先级数据组件时的接收请求，接收到的请求被拒绝。

公开(公告)号：US08352687B2

公开(公告)日：2013-01-08

申请号：US12821726

申请日：2010-06-23

申请人： Deanna Postles Dunn Berger ,  Michael F. Fee ,  Arthur J. O'Neill, Jr. ,  Robert J. Sonnelitter, III

发明人： Deanna Postles Dunn Berger ,  Michael F. Fee ,  Arthur J. O'Neill, Jr. ,  Robert J. Sonnelitter, III

IPC分类号： G06F12/08

CPC分类号： G06F12/0831 ,  G06F12/0811

摘要： A cache includes a cache pipeline, a request receiver configured to receive off chip coherency requests from an off chip cache and a plurality of state machines coupled to the request receiver. The cache also includes an arbiter coupled between the plurality of state machines and the cache pipe line and is configured to give priority to off chip coherency requests as well as a counter configured to count the number of coherency requests sent from the cache pipeline to a lower level cache. The cache pipeline is halted from sending coherency requests when the counter exceeds a predetermined limit.

公开(公告)号：US08327078B2

公开(公告)日：2012-12-04

申请号：US12822884

申请日：2010-06-24

申请人： Deanna Postles Dunn Berger ,  Michael Fee ,  Arthur J. O'Neill, Jr. ,  Robert J. Sonnelitter, III

发明人： Deanna Postles Dunn Berger ,  Michael Fee ,  Arthur J. O'Neill, Jr. ,  Robert J. Sonnelitter, III

IPC分类号： G06F12/00

CPC分类号： G06F12/0888 ,  G06F12/0897 ,  G06F2212/1024

摘要： A computer-implemented method for managing data transfer in a multi-level memory hierarchy that includes receiving a fetch request for allocation of data in a higher level memory, determining whether a data bus between the higher level memory and a lower level memory is available, bypassing an intervening memory between the higher level memory and the lower level memory when it is determined that the data bus is available, and transferring the requested data directly from the higher level memory to the lower level memory.

摘要翻译： 一种用于管理多级存储器层级中的数据传输的计算机实现的方法，包括：接收用于在较高级存储器中分配数据的提取请求，确定所述较高级存储器和较低级存储器之间的数据总线是否可用， 当确定数据总线可用时，绕过高级存储器和较低级存储器之间的中间存储器，并将所请求的数据直接从较高级存储器传送到下级存储器。