公开(公告)号：US20110320722A1

公开(公告)日：2011-12-29

申请号：US12821744

申请日：2010-06-23

申请人： Deanna Postles Dunn Berger ,  Garrett M. Drapala ,  Michael F. Fee ,  Robert J. Sonnelitter, III

发明人： Deanna Postles Dunn Berger ,  Garrett M. Drapala ,  Michael F. Fee ,  Robert J. Sonnelitter, III

IPC分类号： G06F12/08 ,  G06F9/30

CPC分类号： G06F12/084 ,  G06F12/0855

摘要： An apparatus for controlling access to a pipeline includes a plurality of command queues including a first subset of the plurality of command queues being assigned processes the commands of first command type, a second subset of the plurality of command queues being assigned to process commands of the second command type, and a third subset of the plurality of the command queues not being assigned to either the first subset or the second subset. The apparatus also includes an input controller configured to receive requests having the first command type and the second command type and assign requests having the first command type to command queues in the first subset until all command queues in the first subset are filled and then assign requests having the first command type to command queues in the third subset.

摘要翻译： 一种用于控制对流水线的访问的装置，包括多个命令队列，包括被分配处理第一命令类型的命令的多个命令队列的第一子集，多个命令队列的第二子集被分配给 第二命令类型，并且多个命令队列的第三子集未被分配给第一子集或第二子集。 该装置还包括输入控制器，其被配置为接收具有第一命令类型和第二命令类型的请求，并且分配具有第一命令类型的请求来命令第一子集中的队列，直到第一子集中的所有命令队列被填满，然后分配请求 具有第一种命令类型来命令第三个子集中的队列。

公开(公告)号：US08635409B2

公开(公告)日：2014-01-21

申请号：US12821706

申请日：2010-06-23

申请人： Deanna Postles Dunn Berger ,  Michael F. Fee ,  Kenneth D. Klapproth ,  Robert J. Sonnelitter, III

发明人： Deanna Postles Dunn Berger ,  Michael F. Fee ,  Kenneth D. Klapproth ,  Robert J. Sonnelitter, III

IPC分类号： G06F12/08

CPC分类号： G06F12/0855 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0846

摘要： A method of providing requests to a cache pipeline includes receiving a plurality of requests from one or more state machines at an arbiter; selecting one of the plurality of requests as a selected request the selected request having been provided by a first state machine; determining that the selected request includes a mode that requires a first step and a second step, the first step including an access to a location in a cache; determining that the location in the cache is unavailable; and replacing the mode with a modified mode that only includes the second step.

摘要翻译： 向缓存流水线提供请求的方法包括：从仲裁器的一个或多个状态机接收多个请求; 从所选择的请求中选择所述多个请求中的一个请求，所述请求已由第一状态机提供; 确定所选择的请求包括需要第一步骤和第二步骤的模式，所述第一步骤包括对高速缓存中的位置的访问; 确定高速缓存中的位置不可用; 并用仅包括第二步的修改模式替换该模式。

公开(公告)号：US08407420B2

公开(公告)日：2013-03-26

申请号：US12821721

申请日：2010-06-23

申请人： Deanna Postles Dunn Berger ,  Michael F. Fee ,  Robert J. Sonnelitter, III

发明人： Deanna Postles Dunn Berger ,  Michael F. Fee ,  Robert J. Sonnelitter, III

IPC分类号： G06F13/00 ,  G06F12/08

CPC分类号： G06F12/0857 ,  G06F12/084

摘要： A memory system, apparatus and method for performing operations in a shared cache coupled to a first requester and a second requester. The method includes receiving at the shared cache a first request from the second requester; assigning the request to a state machine; transmitting a first pipe pass request from the state machine to an arbiter; providing a first instruction from the first pipe pass request to a cache pipeline, the first instruction causing a first pipe pass; and providing a second pipe pass request to the arbiter before the first pipe pass is completed. The first requester may be a lower level cache such as an L2 cache, or an I/O device and the second requester may be an upper level cache such as an L4 cache, and the first request may be a coherency request.

摘要翻译： 一种用于在耦合到第一请求者和第二请求者的共享高速缓存中执行操作的存储器系统，装置和方法。 该方法包括在共享缓存中接收来自第二请求者的第一请求; 将请求分配给状态机; 将来自状态机的第一管道通过请求发送到仲裁器; 提供从所述第一管道通过请求到高速缓存流水线的第一指令，所述第一指令引起第一管道通过; 以及在第一管道通过完成之前向仲裁者提供第二管道通过请求。 第一请求者可以是诸如L2高速缓存或I / O设备的低级缓存，并且第二请求者可以是诸如L4高速缓存的上级高速缓存，并且第一请求可以是一致性请求。

公开(公告)号：US08352687B2

公开(公告)日：2013-01-08

申请号：US12821726

申请日：2010-06-23

申请人： Deanna Postles Dunn Berger ,  Michael F. Fee ,  Arthur J. O'Neill, Jr. ,  Robert J. Sonnelitter, III

发明人： Deanna Postles Dunn Berger ,  Michael F. Fee ,  Arthur J. O'Neill, Jr. ,  Robert J. Sonnelitter, III

IPC分类号： G06F12/08

CPC分类号： G06F12/0831 ,  G06F12/0811

摘要： A cache includes a cache pipeline, a request receiver configured to receive off chip coherency requests from an off chip cache and a plurality of state machines coupled to the request receiver. The cache also includes an arbiter coupled between the plurality of state machines and the cache pipe line and is configured to give priority to off chip coherency requests as well as a counter configured to count the number of coherency requests sent from the cache pipeline to a lower level cache. The cache pipeline is halted from sending coherency requests when the counter exceeds a predetermined limit.

公开(公告)号：US20110320725A1

公开(公告)日：2011-12-29

申请号：US12821706

申请日：2010-06-23

申请人： Deanna Postles Dunn Berger ,  Michael F. Fee ,  Kenneth D. Klapproth ,  Robert J. Sonnelitter, III

发明人： Deanna Postles Dunn Berger ,  Michael F. Fee ,  Kenneth D. Klapproth ,  Robert J. Sonnelitter, III

IPC分类号： G06F12/08

CPC分类号： G06F12/0855 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0846

摘要： A method of providing requests to a cache pipeline includes receiving a plurality of requests from one or more state machines at an arbiter, selecting one of the plurality of requests as a selected request, the selected request having been provided by a first state machine, determining that the selected request includes a mode that requires a first step and a second step, the first step including an access to a location in a cache, determining that the location in the cache is unavailable, and replacing the mode with a modified mode that only includes the second step.

摘要翻译： 向高速缓存流水线提供请求的方法包括：从仲裁器的一个或多个状态机接收多个请求，将所述多个请求中的一个请求选择为所选择的请求，所选择的请求由第一状态机提供，确定 所选择的请求包括需要第一步骤和第二步骤的模式，第一步骤包括对高速缓存中的位置的访问，确定高速缓存中的位置不可用，并且以仅修改模式替换模式 包括第二步。

公开(公告)号：US20110320694A1

公开(公告)日：2011-12-29

申请号：US12821721

申请日：2010-06-23

申请人： Deanna Postles Dunn Berger ,  Michael F. Fee ,  Robert J. Sonnelitter, III

发明人： Deanna Postles Dunn Berger ,  Michael F. Fee ,  Robert J. Sonnelitter, III

IPC分类号： G06F12/08 ,  G06F12/02

CPC分类号： G06F12/0857 ,  G06F12/084

摘要： A method of performing operations in a shared cache coupled to a first requestor and a second requestor includes receiving at the shared cache a first request from the second requester; assigning the request to a state machine; transmitting a first pipe pass request from the state machine to an arbiter; providing a first instruction from the first pipe pass request to a cache pipeline, the first instruction causing a first pipe pass; and providing a second pipe pass request to the arbiter before the first pipe pass is completed.

摘要翻译： 一种在耦合到第一请求者和第二请求者的共享高速缓存中执行操作的方法包括：在所述共享缓存处接收来自所述第二请求者的第一请求; 将请求分配给状态机; 将来自状态机的第一管道通过请求发送到仲裁器; 提供从所述第一管道通过请求到高速缓存流水线的第一指令，所述第一指令引起第一管道通过; 以及在第一管道通过完成之前向仲裁者提供第二管道通过请求。

公开(公告)号：US08566532B2

公开(公告)日：2013-10-22

申请号：US12821744

申请日：2010-06-23

申请人： Deanna Postles Dunn Berger ,  Garrett M. Drapala ,  Michael F. Fee ,  Robert J. Sonnelitter, III

发明人： Deanna Postles Dunn Berger ,  Garrett M. Drapala ,  Michael F. Fee ,  Robert J. Sonnelitter, III

IPC分类号： G06F12/08

CPC分类号： G06F12/084 ,  G06F12/0855

摘要： An apparatus for controlling access to a pipeline includes a plurality of command queues including a first subset of the plurality of command queues being assigned processes the commands of first command type, a second subset of the plurality of command queues being assigned to process commands of the second command type, and a third subset of the plurality of the command queues not being assigned to either the first subset or the second subset. The apparatus also includes an input controller configured to receive requests having the first command type and the second command type and assign requests having the first command type to command queues in the first subset until all command queues in the first subset are filled and then assign requests having the first command type to command queues in the third subset.

摘要翻译： 一种用于控制对流水线的访问的装置，包括多个命令队列，包括被分配处理第一命令类型的命令的多个命令队列的第一子集，多个命令队列的第二子集被分配给 第二命令类型，并且多个命令队列的第三子集未被分配给第一子集或第二子集。 该装置还包括输入控制器，其被配置为接收具有第一命令类型和第二命令类型的请求，并且分配具有第一命令类型的请求来命令第一子集中的队列，直到第一子集中的所有命令队列被填满，然后分配请求 具有第一种命令类型来命令第三个子集中的队列。

公开(公告)号：US20110320728A1

公开(公告)日：2011-12-29

申请号：US12821726

申请日：2010-06-23

申请人： Deanna Postles Dunn Berger ,  Michael F. Fee ,  Arthur J. O'Neill, JR. ,  Robert J. Sonnelitter, III

发明人： Deanna Postles Dunn Berger ,  Michael F. Fee ,  Arthur J. O'Neill, JR. ,  Robert J. Sonnelitter, III

IPC分类号： G06F12/08

CPC分类号： G06F12/0831 ,  G06F12/0811

摘要： A cache includes a cache pipeline, a request receiver configured to receive off chip coherency requests from an off chip cache and a plurality of state machines coupled to the request receiver. The cache also includes an arbiter coupled between the plurality of state machines and the cache pipe line and is configured to give priority to off chip coherency requests as well as a counter configured to count the number of coherency requests sent from the cache pipeline to a lower level cache. The cache pipeline is halted from sending coherency requests when the counter exceeds a predetermined limit.

摘要翻译： 高速缓存包括高速缓存流水线，被配置为从芯片内高速缓存和多个与所述请求接收器耦合的状态机接收芯片外相关性请求的请求接收器。 高速缓存还包括耦合在多个状态机和高速缓存管线之间的仲裁器，并且被配置为优先考虑片外一致性请求，以及被配置为将从高速缓存流水线发送的一致性请求的数量计数到较低 级缓存。 当计数器超过预定限制时，高速缓存流水线停止发送一致性请求。

公开(公告)号：US09378023B2

公开(公告)日：2016-06-28

申请号：US13495201

申请日：2012-06-13

申请人： Deanna Postles Dunn Berger ,  Michael F. Fee ,  Edward J. Kaminski, Jr. ,  Diane L. Orf

发明人： Deanna Postles Dunn Berger ,  Michael F. Fee ,  Edward J. Kaminski, Jr. ,  Diane L. Orf

IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F9/50 ,  G06F13/16 ,  G06F13/18 ,  G06F9/54 ,  G06F13/14

CPC分类号： G06F9/3836 ,  G06F9/3869 ,  G06F9/544 ,  G06F13/14 ,  G06F13/1605 ,  G06F13/1615 ,  G06F13/1621 ,  G06F13/1652 ,  G06F13/1657 ,  G06F13/1663

摘要： Embodiments relate to cross-pipe serialization for a multi-pipeline computer processor. An aspect includes receiving, by a processor, the processor comprising a first pipeline, the first pipeline comprising a serialization pipeline, and a second pipeline, the second pipeline comprising a non-serialization pipeline, a request comprising a first subrequest for the first pipeline and a second subrequest for the second pipeline. Another aspect includes completing the first subrequest by the first pipeline. Another aspect includes, based on completing the first subrequest by the first pipeline, sending cross-pipe unlock signal from the first pipeline to the second pipeline. Yet another aspect includes, based on receiving the cross-pipe unlock signal by the second pipeline, completing the second subrequest by the second pipeline.

公开(公告)号：US20130339701A1

公开(公告)日：2013-12-19

申请号：US13495201

申请日：2012-06-13

申请人： Deanna Postles Dunn Berger ,  Michael F. Fee ,  Edward J. Kaminski,, JR. ,  Diane L. Orf

发明人： Deanna Postles Dunn Berger ,  Michael F. Fee ,  Edward J. Kaminski,, JR. ,  Diane L. Orf

IPC分类号： G06F9/38

CPC分类号： G06F9/3836 ,  G06F9/3869 ,  G06F9/544 ,  G06F13/14 ,  G06F13/1605 ,  G06F13/1615 ,  G06F13/1621 ,  G06F13/1652 ,  G06F13/1657 ,  G06F13/1663

摘要： Embodiments relate to cross-pipe serialization for a multi-pipeline computer processor. An aspect includes receiving, by a processor, the processor comprising a first pipeline, the first pipeline comprising a serialization pipeline, and a second pipeline, the second pipeline comprising a non-serialization pipeline, a request comprising a first subrequest for the first pipeline and a second subrequest for the second pipeline. Another aspect includes completing the first subrequest by the first pipeline. Another aspect includes, based on completing the first subrequest by the first pipeline, sending cross-pipe unlock signal from the first pipeline to the second pipeline. Yet another aspect includes, based on receiving the cross-pipe unlock signal by the second pipeline, completing the second subrequest by the second pipeline.

摘要翻译： 实施例涉及用于多管线计算机处理器的跨管道串行化。 一个方面包括由处理器接收处理器，该处理器包括第一流水线，第一流水线包括串行化流水线和第二流水线，第二流水线包括非串行流水线，包括第一流水线的第一子请求的请求和 第二个管道的第二个子请求。 另一方面包括通过第一管道完成第一个子请求。 另一方面包括，基于通过第一管道完成第一子请求，将第一管道的跨管解锁信号发送到第二管道。 另一方面包括，基于通过第二管线接收横管解锁信号，通过第二管道完成第二子请求。