公开(公告)号：US20090006693A1

公开(公告)日：2009-01-01

申请号：US11768934

申请日：2007-06-27

申请人： Deanna P. Dunn ,  Christine C. Jones ,  Arthur J. O'Neill ,  Vesselina K. Papazova ,  Robert J. Sonnelitter, III ,  Craig R. Walters

发明人： Deanna P. Dunn ,  Christine C. Jones ,  Arthur J. O'Neill ,  Vesselina K. Papazova ,  Robert J. Sonnelitter, III ,  Craig R. Walters

IPC分类号： G06F13/14

CPC分类号： G06F13/14 ,  G06F9/50 ,  G06F2209/5021 ,  Y02D10/14 ,  Y02D10/22

摘要： A modification of rank priority arbitration for access to computer system resources through a shared pipeline that provides more equitable arbitration by allowing a higher ranked request access to the shared resource ahead of a lower ranked requester only one time. If multiple requests are active at the same time, the rank priority will first select the highest priority active request and grant it access to the resource. It will also set a ‘blocking latch’ to prevent that higher priority request from re-gaining access to the resource until the rest of the outstanding lower priority active requesters have had a chance to access the resource.

摘要翻译： 通过共享流水线访问计算机系统资源的等级优先仲裁的修改，通过允许较高排名的请求仅在较低等级的请求者之前访问共享资源，提供更公平的仲裁。 如果多个请求同时处于活动状态，则排名优先级将首先选择最高优先级的活动请求并授予对资源的访问权限。 它还将设置一个“阻塞锁定”，以防止更高优先级的请求重新获得对资源的访问，直到其余的优先级较低的主动请求者有机会访问该资源。

公开(公告)号：US08521960B2

公开(公告)日：2013-08-27

申请号：US12821736

申请日：2010-06-23

申请人： Deanna P. Berger ,  Michael F. Fee ,  Christine C. Jones ,  Arthur J. O'Neill ,  Diana L. Orf ,  Robert J. Sonnelitter, III

发明人： Deanna P. Berger ,  Michael F. Fee ,  Christine C. Jones ,  Arthur J. O'Neill ,  Diana L. Orf ,  Robert J. Sonnelitter, III

IPC分类号： G06F12/00

CPC分类号： G06F12/0857 ,  G06F12/084 ,  G06F12/0846 ,  G06F12/0855 ,  G06F2212/1024 ,  G06F2212/281

摘要： A method, information processing device, and computer program product mitigate busy time in a hierarchical store-through memory cache structure. In one embodiment, a cache directory associated with a memory cache is divided into a plurality of portions each associated with a portion memory cache. Simultaneous cache lookup operations and cache write operations between the plurality of portions of the cache directory are supported. Two or more store commands are simultaneously processed in a shared cache pipeline communicatively coupled to the plurality of portions of the cache directory.

摘要翻译： 一种方法，信息处理设备和计算机程序产品减轻分层存储到存储器高速缓存结构中的忙时间。 在一个实施例中，与存储器高速缓存相关联的高速缓存目录被分成多个部分，每个部分与部分存储器高速缓存相关联。 支持高速缓存目录的多个部分之间的同时高速缓存查找操作和缓存写入操作。 在通信地耦合到高速缓存目录的多个部分的共享高速缓存管道中同时处理两个或更多个存储命令。

公开(公告)号：US20110320695A1

公开(公告)日：2011-12-29

申请号：US12821736

申请日：2010-06-23

申请人： Deanna P. BERGER ,  Michael F. Fee ,  Christine C. Jones ,  Arthur J. O'Neill ,  Diana L. Orf ,  Robert J. Sonnelitter, III

发明人： Deanna P. BERGER ,  Michael F. Fee ,  Christine C. Jones ,  Arthur J. O'Neill ,  Diana L. Orf ,  Robert J. Sonnelitter, III

IPC分类号： G06F12/08 ,  G06F12/00

CPC分类号： G06F12/0857 ,  G06F12/084 ,  G06F12/0846 ,  G06F12/0855 ,  G06F2212/1024 ,  G06F2212/281

摘要： Various embodiments of the present invention mitigate busy time in a hierarchical store-through memory cache structure. In one embodiment, a cache directory associated with a memory cache is divided into a plurality of portions each associated with a portion memory cache. Simultaneous cache lookup operations and cache write operations between the plurality of portions of the cache directory are supported. Two or more store commands are simultaneously processed in a shared cache pipeline communicatively coupled to the plurality of portions of the cache directory.

摘要翻译： 本发明的各种实施例减轻了分级存储器存储器高速缓存结构中的繁忙时间。 在一个实施例中，与存储器高速缓存相关联的高速缓存目录被分成多个部分，每个部分与部分存储器高速缓存相关联。 支持高速缓存目录的多个部分之间的同时高速缓存查找操作和缓存写入操作。 在通信地耦合到高速缓存目录的多个部分的共享高速缓存管道中同时处理两个或更多个存储命令。

公开(公告)号：US08671267B2

公开(公告)日：2014-03-11

申请号：US12822359

申请日：2010-06-24

申请人： Ekaterina M. Ambroladze ,  Deanna Postles Dunn Berger ,  Michael Fee ,  Christine C. Jones ,  Arthur J. O'Neill, Jr. ,  Diana Lynn Orf ,  Robert J. Sonnelitter, III

发明人： Ekaterina M. Ambroladze ,  Deanna Postles Dunn Berger ,  Michael Fee ,  Christine C. Jones ,  Arthur J. O'Neill, Jr. ,  Diana Lynn Orf ,  Robert J. Sonnelitter, III

IPC分类号： G06F9/30 ,  G06F9/40 ,  G06F13/00 ,  G06F3/00

CPC分类号： G06F9/3867 ,  G06F11/3419 ,  G06F11/3466 ,  G06F2201/88

摘要： A pipelined processing device includes: a device controller configured to receive a request to perform an operation; a plurality of subcontrollers configured to receive at least one instruction associated with the operation, each of the plurality of subcontrollers including a counter configured to generate an active time value indicating at least a portion of a time taken to process the at least one instruction; a pipeline processor configured to receive and process the at least one instruction, the pipeline processor configured to receive the active time value; and a shared pipeline storage area configured to store the active time value for each of the plurality of subcontrollers.

摘要翻译： 流水线处理装置包括：设备控制器，被配置为接收执行操作的请求; 多个子控制器被配置为接收与所述操作相关联的至少一个指令，所述多个子控制器中的每一个包括配置成生成指示处理所述至少一个指令所花费的时间的至少一部分的活动时间值的计数器; 流水线处理器，被配置为接收和处理所述至少一个指令，所述流水线处理器被配置为接收所述活动时间值; 以及共享流水线存储区域，被配置为存储多个子控制器中的每一个的活动时间值。

公开(公告)号：US20110320779A1

公开(公告)日：2011-12-29

申请号：US12822359

申请日：2010-06-24

申请人： Ekaterina M. Ambroladze ,  Deanna Postles Dunn Berger ,  Michael Fee ,  Christine C. Jones ,  Arthur J. O'Neill, JR. ,  Diana L. Orf ,  Robert J. Sonnelitter, III

发明人： Ekaterina M. Ambroladze ,  Deanna Postles Dunn Berger ,  Michael Fee ,  Christine C. Jones ,  Arthur J. O'Neill, JR. ,  Diana L. Orf ,  Robert J. Sonnelitter, III

IPC分类号： G06F9/30

CPC分类号： G06F9/3867 ,  G06F11/3419 ,  G06F11/3466 ,  G06F2201/88

摘要： A pipelined processing device includes: a device controller configured to receive a request to perform an operation; a plurality of subcontrollers configured to receive at least one instruction associated with the operation, each of the plurality of subcontrollers including a counter configured to generate an active time value indicating at least a portion of a time taken to process the at least one instruction; a pipeline processor configured to receive and process the at least one instruction, the pipeline processor configured to receive the active time value; and a shared pipeline storage area configured to store the active time value for each of the plurality of subcontrollers.

摘要翻译： 流水线处理装置包括：设备控制器，被配置为接收执行操作的请求; 多个子控制器被配置为接收与所述操作相关联的至少一个指令，所述多个子控制器中的每一个包括配置成生成指示处理所述至少一个指令所花费的时间的至少一部分的活动时间值的计数器; 流水线处理器，被配置为接收和处理所述至少一个指令，所述流水线处理器被配置为接收所述活动时间值; 以及共享流水线存储区域，被配置为存储多个子控制器中的每一个的活动时间值。

公开(公告)号：US08447932B2

公开(公告)日：2013-05-21

申请号：US12820511

申请日：2010-06-22

申请人： Deanna P. Berger ,  Michael F. Fee ,  Christine C. Jones ,  Diana L. Orf ,  Robert J. Sonnelitter, III

发明人： Deanna P. Berger ,  Michael F. Fee ,  Christine C. Jones ,  Diana L. Orf ,  Robert J. Sonnelitter, III

IPC分类号： G06F12/12

CPC分类号： G06F11/1064 ,  G06F12/0802

摘要： Various embodiments of the present invention merge data in a cache memory. In one embodiment a set of store data is received from a processing core. A store merge command and a merge mask from are also received from the processing core. A portion of the store data to perform a merging operation thereon is identified based on the store merge command. A sub-portion of the portion of the store data to be merged with a corresponding set of data from a cache memory is identified based on the merge mask. The sub-portion is merged with the corresponding set of data from the cache memory.

摘要翻译： 本发明的各种实施例将数据合并在高速缓冲存储器中。 在一个实施例中，从处理核心接收一组存储数据。 还从处理核心接收存储合并命令和合并掩码。 基于存储合并命令来识别用于执行其上的合并操作的存储数据的一部分。 基于合并掩码来识别与高速缓冲存储器的相应的数据集合合并的存储数据的一部分的子部分。 子部分与来自高速缓冲存储器的相应的数据集合合并。

公开(公告)号：US20110314211A1

公开(公告)日：2011-12-22

申请号：US12820511

申请日：2010-06-22

申请人： Deanna P. BERGER ,  Michael F. Fee ,  Christine C. Jones ,  Diana L. Orf ,  Robert J. Sonnelitter, III

发明人： Deanna P. BERGER ,  Michael F. Fee ,  Christine C. Jones ,  Diana L. Orf ,  Robert J. Sonnelitter, III

IPC分类号： G06F12/08 ,  G06F12/02

CPC分类号： G06F11/1064 ,  G06F12/0802

摘要： Various embodiments of the present invention merge data in a cache memory. In one embodiment a set of store data is received from a processing core. A store merge command and a merge mask from are also received from the processing core. A portion of the store data to perform a merging operation thereon is identified based on the store merge command. A sub-portion of the portion of the store data to be merged with a corresponding set of data from a cache memory is identified based on the merge mask. The sub-portion is merged with the corresponding set of data from the cache memory.

摘要翻译： 本发明的各种实施例将数据合并在高速缓冲存储器中。 在一个实施例中，从处理核心接收一组存储数据。 还从处理核心接收存储合并命令和合并掩码。 基于存储合并命令来识别用于执行其上的合并操作的存储数据的一部分。 基于合并掩码来识别与高速缓冲存储器的相应的数据集合合并的存储数据的一部分的子部分。 子部分与来自高速缓冲存储器的相应的数据集合合并。

公开(公告)号：US08447930B2

公开(公告)日：2013-05-21

申请号：US12820528

申请日：2010-06-22

申请人： Deanna P. Berger ,  Michael F. Fee ,  Christine C. Jones ,  Diana L. Orf ,  Robert J. Sonnelitter, III

发明人： Deanna P. Berger ,  Michael F. Fee ,  Christine C. Jones ,  Diana L. Orf ,  Robert J. Sonnelitter, III

IPC分类号： G06F12/14

CPC分类号： G06F12/0811 ,  G06F9/524 ,  G06F12/0855 ,  G06F12/0897

摘要： Various embodiments of the present invention manage a hierarchical store-through memory cache structure. A store request queue is associated with a processing core in multiple processing cores. At least one blocking condition is determined to have occurred at the store request queue. Multiple non-store requests and a set of store requests associated with a remaining set of processing cores in the multiple processing cores are dynamically blocked from accessing a memory cache in response to the blocking condition having occurred.

公开(公告)号：US20110314212A1

公开(公告)日：2011-12-22

申请号：US12820528

申请日：2010-06-22

申请人： DEANNA P. BERGER ,  Michael F. Fee ,  Christine C. Jones ,  Diana L. Orf ,  Robert J. Sonnelitter, III

发明人： DEANNA P. BERGER ,  Michael F. Fee ,  Christine C. Jones ,  Diana L. Orf ,  Robert J. Sonnelitter, III

IPC分类号： G06F12/08 ,  G06F12/02

CPC分类号： G06F12/0811 ,  G06F9/524 ,  G06F12/0855 ,  G06F12/0897

摘要： Various embodiments of the present invention manage a hierarchical store-through memory cache structure. A store request queue is associated with a processing core in multiple processing cores. At least one blocking condition is determined to have occurred at the store request queue. Multiple non-store requests and a set of store requests associated with a remaining set of processing cores in the multiple processing cores are dynamically blocked from accessing a memory cache in response to the blocking condition having occurred.

摘要翻译： 本发明的各种实施例管理分层存储存储器高速缓存结构。 存储请求队列与多个处理核心中的处理核心相关联。 确定至少一个阻塞条件已经在存储请求队列中发生。 响应于发生的阻塞状态，多个非存储请求和与多个处理核心中的剩余处理核心集相关联的一组存储请求被动态阻止访问存储器高速缓存。

公开(公告)号：US20130339593A1

公开(公告)日：2013-12-19

申请号：US13523523

申请日：2012-06-14

申请人： Michael F. Fee ,  Christine C. Jones ,  Arthur J. O'Neill ,  Diane L. Orf

发明人： Michael F. Fee ,  Christine C. Jones ,  Arthur J. O'Neill ,  Diane L. Orf

IPC分类号： G06F12/00 ,  G06F12/08

CPC分类号： G06F12/0864 ,  G06F9/3824 ,  G06F12/0846 ,  G06F12/0855 ,  Y02D10/13

摘要： A computer program product for reducing penalties for cache accessing operations is provided. The computer program product includes a tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method. The method includes respectively associating platform registers with cache arrays, loading control information and data of a store operation to be executed with respect to one or more of the cache arrays into the one or more of the platform registers respectively associated with the one or more of the cache arrays, and, based on the one or more of the cache arrays becoming available, committing the data from the one or more of the platform registers using the control information from the same platform registers to the one or more of the cache arrays.

摘要翻译： 提供了用于减少高速缓存访​​问操作的惩罚的计算机程序产品。 计算机程序产品包括可由处理电路读取的有形存储介质，并且存储由处理电路执行以执行方法的指令。 该方法包括分别将平台寄存器与高速缓存阵列相关联，将控制信息和关于一个或多个高速缓存阵列执行的存储操作的数据加载到分别与一个或多个缓存阵列中的一个或多个 缓存阵列，并且基于一个或多个缓存阵列变得可用，使用来自相同平台寄存器的控制信息将一个或多个平台寄存器中的数据提交到一个或多个缓存阵列。