公开(公告)号：US08747023B1

公开(公告)日：2014-06-10

申请号：US13564056

申请日：2012-08-01

Applicant: Robert Walker

Inventor： Robert Walker

IPC: E02B3/06

CPC classification number: E02B3/06 ,  E02B3/046 ,  E02B3/062

Abstract: A wave break structure having a body with a bulkhead and a first pontoon and a second pontoon. The first pontoon is positioned on one side of the bulkhead and the second pontoon is positioned on the opposite side of the bulkhead. The bulkhead extends substantially above the first and second pontoons. The bulkhead and the pontoons are integrally formed together of a metallic material. The bulkhead having a first wall extending at least 45° with respect to a second wall of said bulkhead so as to have an inverted V-shaped configuration. A crushed stone coating is applied to a surface of the bulkhead.

Abstract translation: 一种波纹结构，具有具有舱壁的主体和第一浮筒以及第二浮筒。 第一个浮筒位于隔板的一侧，第二个浮筒位于隔板的相对侧。 舱壁基本上在第一和第二浮船的上方延伸。 隔板和浮体由金属材料一体地形成在一起。 隔板具有相对于所述隔板的第二壁延伸至少45°的第一壁，以具有倒V形构造。 将破碎的石材涂层施加到隔板的表面。

公开(公告)号：US08621408B2

公开(公告)日：2013-12-31

申请号：US13438602

申请日：2012-04-03

Applicant: Mahesh A. Iyer ,  Robert Walker ,  Sudipto Kundu

Inventor： Mahesh A. Iyer ,  Robert Walker ,  Sudipto Kundu

IPC: G06F17/50

CPC classification number: G06F17/505 ,  G06F2217/84

Abstract: Systems and techniques for optimizing a circuit design are described. Some embodiments reduce the number of gates in the library (e.g., by dynamically pruning the library) which are considered for optimization. Some embodiments create a linear delay model, and use the linear delay model instead of a non-linear delay model to substantially reduce the amount of computation required to check whether or not a particular replacement gate improves one or more metrics of the circuit design. Some embodiments determine an order for processing the gates in the library or for processing input pins of a gate to facilitate early rejection of a candidate gate in the library of gates. In some embodiments, the evaluation of the impact of a candidate gate transformation is done progressively and level-by-level only up to the point where the gate transformation degrades one or more metrics.

Abstract translation: 描述了用于优化电路设计的系统和技术。 一些实施例减少库中的门数（例如，通过动态修剪库），这被考虑用于优化。 一些实施例创建线性延迟模型，并且使用线性延迟模型而不是非线性延迟模型来基本上减少检查特定替换门是否改善电路设计的一个或多个度量所需的计算量。 一些实施例确定用于处理库中的门或用于处理门的输入引脚的顺序，以便于早期拒绝门库中的候选门。 在一些实施例中，候选门转换的影响的评估逐渐地逐级地逐级地进行，直到门转换降级一个或多个度量为止。

公开(公告)号：US08595447B2

公开(公告)日：2013-11-26

申请号：US13561922

申请日：2012-07-30

Applicant: Robert Walker

Inventor： Robert Walker

IPC: G06F12/00

CPC classification number: G06F13/1663 ,  G06F2213/0038

Abstract: Systems, methods of operating a memory device, and methods of arbitrating access to a memory array in a memory device having an internal processor are provided. In one or more embodiments, conflicts in accessing the memory array are reduced by interfacing an external processor, such as a memory controller, with the internal processor, which could be an embedded ALU, through a control interface. The external processor can control access to the memory array, and the internal processor can send signals to the external processor to request access to the memory array. The signals may also request a particular bank in the memory array. In different embodiments, the external processor and the internal processor communicate via the control interface or a standard memory interface to grant access to the memory array, or to a particular bank in the memory array, for example.

Abstract translation: 提供了操作存储器件的系统，方法以及对具有内部处理器的存储器件中的存储器阵列的访问的方法。 在一个或多个实施例中，通过通过控制接口将诸如存储器控制器的外部处理器与内部处理器（其可以是嵌入式ALU）进行接口来减少访问存储器阵列的冲突。 外部处理器可以控制对存储器阵列的访问，并且内部处理器可以向外部处理器发送信号以请求访问存储器阵列。 信号还可以请求存储器阵列中的特定存储体。 在不同的实施例中，外部处理器和内部处理器通过控制接口或标准存储器接口进行通信，例如授予对存储器阵列或存储器阵列中的特定存储体的访问。

公开(公告)号：US20130304531A1

公开(公告)日：2013-11-14

申请号：US13469318

申请日：2012-05-11

Applicant: Paul Barber ,  Robert Walker ,  Geoffrey Ng ,  Jason Seeley

Inventor： Paul Barber ,  Robert Walker ,  Geoffrey Ng ,  Jason Seeley

IPC: G06Q10/06

CPC classification number: G06Q10/06

Abstract: A system, method and computer program product for performing detailed planning functions for businesses, enterprises and other types of organizations. According to an embodiment, the system comprises a graphical user interface configured to allow a user to define calculations based on data associated with an entity that may have scalar attributes for each entity, and/or a time series, and execution of the defined calculation generates time series result. According to another aspect, a calculation definition may be configured to be adjustable allowing a user to adjust parameter value(s) for each entity associated with the calculation definition. According to another aspect, a calculation definition may be configured to be discretionary allowing a user to attach or assign a calculation to each entity individually. According to another aspect, multiple calculations may be created and have the same name.

Abstract translation: 一种用于为企业，企业和其他类型组织执行详细规划功能的系统，方法和计算机程序产品。 根据实施例，系统包括图形用户界面，其被配置为允许用户基于与可能具有每个实体的标量属性的实体相关联的数据和/或时间序列来定义计算，并且执行所定义的计算生成 时间序列结果。 根据另一方面，计算定义可以被配置为可调节的，以允许用户调整与计算定义相关联的每个实体的参数值。 根据另一方面，计算定义可以被配置为任意允许用户单独地附加或分配给每个实体的计算。 根据另一方面，可以创建多个计算并具有相同的名称。

公开(公告)号：US08521958B2

公开(公告)日：2013-08-27

申请号：US12478457

申请日：2009-06-04

Applicant: Robert Walker

Inventor： Robert Walker

IPC: G06F13/28

CPC classification number: G11C19/00 ,  G06F9/3877 ,  G06F15/7821 ,  G06F15/785 ,  Y02D10/12 ,  Y02D10/13

Abstract: One or more of the present techniques provide a compute engine buffer configured to maneuver data and increase the efficiency of a compute engine. One such compute engine buffer is connected to a compute engine which performs operations on operands retrieved from the buffer, and stores results of the operations to the buffer. Such a compute engine buffer includes a compute buffer having storage units which may be electrically connected or isolated, based on the size of the operands to be stored and the configuration of the compute engine. The compute engine buffer further includes a data buffer, which may be a simple buffer. Operands may be copied to the data buffer before being copied to the compute buffer, which may save additional clock cycles for the compute engine, further increasing the compute engine efficiency.

Abstract translation: 一种或多种本技术提供了一种配置成操纵数据并提高计算引擎效率的计算引擎缓冲器。 一个这样的计算引擎缓冲器连接到计算引擎，该计算引擎对从缓冲器检索的操作数执行操作，并将操作的结果存储到缓冲器。 这样的计算引擎缓冲器包括基于要存储的操作数的大小和计算引擎的配置的具有可以电连接或隔离的存储单元的计算缓冲器。 计算引擎缓冲器还包括数据缓冲器，其可以是简单缓冲器。 在复制到计算缓冲区之前，操作数可以复制到数据缓冲区，这可能为计算引擎节省额外的时钟周期，进一步提高了计算引擎的效率。

公开(公告)号：US20130145336A1

公开(公告)日：2013-06-06

申请号：US13438602

申请日：2012-04-03

Applicant: Mahesh A. Iyer ,  Robert Walker ,  Sudipto Kundu

Inventor： Mahesh A. Iyer ,  Robert Walker ,  Sudipto Kundu

IPC: G06F17/50

CPC classification number: G06F17/505 ,  G06F2217/84

Abstract: Systems and techniques for optimizing a circuit design are described. Some embodiments reduce the number of gates in the library (e.g., by dynamically pruning the library) which are considered for optimization. Some embodiments create a linear delay model, and use the linear delay model instead of a non-linear delay model to substantially reduce the amount of computation required to check whether or not a particular replacement gate improves one or more metrics of the circuit design. Some embodiments determine an order for processing the gates in the library or for processing input pins of a gate to facilitate early rejection of a candidate gate in the library of gates. In some embodiments, the evaluation of the impact of a candidate gate transformation is done progressively and level-by-level only up to the point where the gate transformation degrades one or more metrics.

Abstract translation: 描述了用于优化电路设计的系统和技术。 一些实施例减少库中的门数（例如，通过动态修剪库），这被考虑用于优化。 一些实施例创建线性延迟模型，并且使用线性延迟模型而不是非线性延迟模型来基本上减少检查特定替换门是否改善电路设计的一个或多个度量所需的计算量。 一些实施例确定用于处理库中的门或用于处理门的输入引脚的顺序，以便于早期拒绝门库中的候选门。 在一些实施例中，候选门转换的影响的评估逐渐地逐级地逐级地进行，直到门转换降级一个或多个度量为止。

公开(公告)号：US08418116B2

公开(公告)日：2013-04-09

申请号：US12697168

申请日：2010-01-29

Applicant: Robert Walker ,  Mahesh A. Iyer ,  Amir H. Mottaez

Inventor： Robert Walker ,  Mahesh A. Iyer ,  Amir H. Mottaez

IPC: G06F17/50

CPC classification number: G06F17/505 ,  G06F17/5031 ,  G06F17/5081

Abstract: Some embodiments of the present invention provide techniques and systems for efficiently optimizing a circuit design for one or more multi-mode multi-corner (MCMM) scenarios. A system can select an optimizing transformation for a logic gate, which if applied to the logic gate, does not degrade a timing metric in a local context of the logic gate. Next, the system can determine whether applying the optimizing transformation to the logic gate degrades the timing metric in a zone around the logic gate. If so, the system can reject the optimizing transformation. Otherwise, the system can determine whether applying the optimizing transformation to the logic gate degrades the timing metric in the circuit design. If so, the system can reject the optimizing transformation. Otherwise, the system can accept the optimizing transformation.

Abstract translation: 本发明的一些实施例提供用于有效地优化一个或多个多模式多角（MCMM）场景的电路设计的技术和系统。 系统可以选择用于逻辑门的优化变换，其如果应用于逻辑门，则不降低逻辑门的本地上下文中的定时度量。 接下来，系统可以确定将优化变换应用于逻辑门是否会降低逻辑门周围区域中的定时度量。 如果是这样，系统可以拒绝优化转换。 否则，系统可以确定将优化变换应用于逻辑门是否会降低电路设计中的定时度量。 如果是这样，系统可以拒绝优化转换。 否则，系统可以接受优化转换。

公开(公告)号：US08111534B2

公开(公告)日：2012-02-07

申请号：US13109852

申请日：2011-05-17

Applicant: Robert Walker

Inventor： Robert Walker

IPC: G11C5/00 ,  G11C7/00 ,  G11C8/00

CPC classification number: G11C8/04 ,  G11C5/066 ,  G11C8/12 ,  G11C8/16

Abstract: Methods, memory devices, and systems are disclosed, such as those for accessing a memory circuit through the use of reduced external pins. With one such system, a single external pin receives a global memory select signal which transmits an access signal for one of a plurality of memory circuits in a system. The memory circuits may be stacked and may also be ranked memory circuits. The global memory select signal may be sent to a counter. Such a counter could count the length of time that the global memory select signal is active, and based on the counting, sends a count signal to a comparator. The comparator may compare the count signal with a programmed value to determine if a specific memory chip and/or port is to be accessed. This configuration may be duplicated over multiple ports on the same memory device, as well as across multiple memory ranks.

Abstract translation: 公开了方法，存储器件和系统，例如通过使用减少的外部引脚来访问存储器电路的方法。 利用一个这样的系统，单个外部引脚接收全局存储器选择信号，该信号发送系统中的多个存储器电路之一的存取信号。 存储器电路可以被堆叠，并且还可以被分级存储器电路。 全局存储器选择信号可以发送到计数器。 这样的计数器可以计算全局存储器选择信号有效的时间长度，并且基于计数，向比较器发送计数信号。 比较器可以将计数信号与编程值进行比较，以确定是否访问特定的存储器芯片和/或端口。 该配置可能会在同一内存设备上的多个端口以及多个内存等级之间复制。

公开(公告)号：US20100312997A1

公开(公告)日：2010-12-09

申请号：US12478412

申请日：2009-06-04

Applicant: Robert Walker

Inventor： Robert Walker

IPC: G06F9/302

CPC classification number: G06F15/7842 ,  G06F9/3001 ,  Y02D10/13

Abstract: Systems, internal processors, and methods of parallel data processing in an internal processor are provided. In one embodiment, an external controller sends instructions to a memory device, and the internal processor on the memory device executes the instructions on the data. The internal processor may include one or more arithmetic logic units (ALUs), and each ALU may perform an operation on an entire operand, such that one or more operands may be processed in parallel by one or more ALUs in the internal processor. The operations may be completed on each operand in one or more cycles through the circuitry of the ALU, and the path of the operands through the ALU may be based on the width of the ALU, the size of the operands, or the type of operation to be performed.

Abstract translation: 提供了内部处理器中的系统，内部处理器和并行数据处理方法。 在一个实施例中，外部控制器向存储器件发送指令，并且存储器设备上的内部处理器执行关于数据的指令。 内部处理器可以包括一个或多个算术逻辑单元（ALU），并且每个ALU可以在整个操作数上执行操作，使得一个或多个操作数可以由内部处理器中的一个或多个ALU并行处理。 可以通过ALU的电路在一个或多个周期中在每个操作数上完成操作，并且通过ALU的操作数的路径可以基于ALU的宽度，操作数的大小或操作的类型 被执行。

公开(公告)号：US20100312990A1

公开(公告)日：2010-12-09

申请号：US12478465

申请日：2009-06-04

Applicant: Robert Walker

Inventor： Robert Walker

IPC: G06F15/76 ,  G06F12/00 ,  G06F9/02

CPC classification number: G06F13/1663 ,  G06F2213/0038

Abstract: Systems, methods of operating a memory device, and methods of arbitrating access to a memory array in a memory device having an internal processor are provided. In one or more embodiments, conflicts in accessing the memory array are reduced by interfacing an external processor, such as a memory controller, with the internal processor, which could be an embedded ALU, through a control interface. The external processor can control access to the memory array, and the internal processor can send signals to the external processor to request access to the memory array. The signals may also request a particular bank in the memory array. In different embodiments, the external processor and the internal processor communicate via the control interface or a standard memory interface to grant access to the memory array, or to a particular bank in the memory array, for example.

Abstract translation: 提供了操作存储器件的系统，方法以及对具有内部处理器的存储器件中的存储器阵列的访问的方法。 在一个或多个实施例中，通过通过控制接口将诸如存储器控制器的外部处理器与内部处理器（其可以是嵌入式ALU）进行接口来减少访问存储器阵列的冲突。 外部处理器可以控制对存储器阵列的访问，并且内部处理器可以向外部处理器发送信号以请求访问存储器阵列。 信号还可以请求存储器阵列中的特定存储体。 在不同的实施例中，外部处理器和内部处理器通过控制接口或标准存储器接口进行通信，例如授予对存储器阵列或存储器阵列中的特定存储体的访问。