公开(公告)号：US06937066B2

公开(公告)日：2005-08-30

申请号：US10336502

申请日：2003-01-03

申请人： John D. Porter ,  Dean D. Gans ,  Larren G. Weber

发明人： John D. Porter ,  Dean D. Gans ,  Larren G. Weber

IPC分类号： H03K19/017

CPC分类号： H03K19/01721

摘要： The invention includes digital logic devices with extremely skewed trip points and reset circuitry for rapidly propagating signal edges. Embodiments of skewed logic devices in accordance with the present invention include inverters, buffers, NOR gates and NAND gates for rapidly propagating a selected “fast” edge of an input signal. Additional embodiments include pulse stretchers, memory devices, substrates, computer systems and methods incorporating the skewed logic devices of the present invention. Each embodiment of a skewed logic device of the present invention is configured to propagate either a fast rising edge or fast falling edge of an output signal, i.e., the “fast” edge, at rates comparable to those of domino logic. An advantage of the skewed logic devices of the present invention over conventional CMOS logic devices is rapid edge propagation. Additionally, virtually all of the input gate loading is devoted to the fast edge being propagated. Additionally, the reset networks, as disclosed herein, are buffered by at least two gates, thus reducing loading seen by the input or the output of the skewed logic device.

公开(公告)号：US06919735B2

公开(公告)日：2005-07-19

申请号：US10336359

申请日：2003-01-03

申请人： John D. Porter ,  Dean D. Gans ,  Larren G. Weber

发明人： John D. Porter ,  Dean D. Gans ,  Larren G. Weber

IPC分类号： H03K19/017 ,  H03K19/0175

CPC分类号： H03K19/01721

摘要： The invention includes digital logic devices with extremely skewed trip points and reset circuitry for rapidly propagating signal edges. Embodiments of skewed logic devices in accordance with the present invention include inverters, buffers, NOR gates and NAND gates for rapidly propagating a selected “fast” edge of an input signal. Additional embodiments include pulse stretchers, memory devices, substrates, computer systems and methods incorporating the skewed logic devices of the present invention. Each embodiment of a skewed logic device of the present invention is configured to propagate either a fast rising edge or fast falling edge of an output signal, i.e., the “fast” edge, at rates comparable to those of domino logic. An advantage of the skewed logic devices of the present invention over conventional CMOS logic devices is rapid edge propagation. Additionally, virtually all of the input gate loading is devoted to the fast edge being propagated. Additionally, the reset networks, as disclosed herein, are buffered by at least two gates, thus reducing loading seen by the input or the output of the skewed logic device.

摘要翻译： 本发明包括具有非常偏斜的跳变点的数字逻辑器件和用于快速传播信号边缘的复位电路。 根据本发明的偏斜逻辑器件的实施例包括用于快速传播输入信号的所选择的“快速”边沿的反相器，缓冲器，或非门和“与非”门。 另外的实施例包括脉冲展开器，存储器件，衬底，计算机系统和结合本发明的倾斜逻辑器件的方法。 本发明的倾斜逻辑器件的每个实施例被配置为以与多米诺逻辑的速率相当的速率传播输出信号的快速上升沿或快速下降沿，即“快速”边沿。 与传统CMOS逻辑器件相比，本发明的偏斜逻辑器件的优点是快速的边沿传播。 此外，实际上所有的输入门加载都用于传播的快速边缘。 此外，如本文所公开的复位网络由至少两个门缓冲，从而减少由倾斜逻辑器件的输入或输出所看到的负载。

公开(公告)号：US06891398B2

公开(公告)日：2005-05-10

申请号：US10336357

申请日：2003-01-03

申请人： John D. Porter ,  Dean D. Gans ,  Larren G. Weber

发明人： John D. Porter ,  Dean D. Gans ,  Larren G. Weber

IPC分类号： H03K19/017 ,  H03K19/0175

CPC分类号： H03K19/01721

摘要： The invention includes digital logic devices with extremely skewed trip points and reset circuitry for rapidly propagating signal edges. Embodiments of skewed logic devices in accordance with the present invention include inverters, buffers, NOR gates and NAND gates for rapidly propagating a selected “fast” edge of an input signal. Additional embodiments include pulse stretchers, memory devices, substrates, computer systems and methods incorporating the skewed logic devices of the present invention. Each embodiment of a skewed logic device of the present invention is configured to propagate either a fast rising edge or fast falling edge of an output signal, i.e., the “fast” edge, at rates comparable to those of domino logic. An advantage of the skewed logic devices of the present invention over conventional CMOS logic devices is rapid edge propagation. Additionally, virtually all of the input gate loading is devoted to the fast edge being propagated. Additionally, the reset networks, as disclosed herein, are buffered by at least two gates, thus reducing loading seen by the input or the output of the skewed logic device.

摘要翻译： 本发明包括具有非常偏斜的跳变点的数字逻辑器件和用于快速传播信号边缘的复位电路。 根据本发明的偏斜逻辑器件的实施例包括用于快速传播输入信号的所选择的“快速”边沿的反相器，缓冲器，或非门和“与非”门。 另外的实施例包括脉冲展开器，存储器件，衬底，计算机系统和结合本发明的倾斜逻辑器件的方法。 本发明的倾斜逻辑器件的每个实施例被配置为以与多米诺逻辑的速率相当的速率传播输出信号的快速上升沿或快速下降沿，即“快速”边沿。 与传统CMOS逻辑器件相比，本发明的偏斜逻辑器件的优点是快速的边沿传播。 此外，实际上所有的输入门加载都用于传播的快速边缘。 此外，如本文所公开的复位网络由至少两个门缓冲，从而减少由倾斜逻辑器件的输入或输出所看到的负载。

公开(公告)号：US06812636B2

公开(公告)日：2004-11-02

申请号：US09823815

申请日：2001-03-30

申请人： John D. Porter ,  Roger A. Pearson ,  Kazuo Kajiwara ,  Haruo Kato ,  Lawrence S. Pan ,  Shiyou Pei ,  Theodore S. Fahlen

发明人： John D. Porter ,  Roger A. Pearson ,  Kazuo Kajiwara ,  Haruo Kato ,  Lawrence S. Pan ,  Shiyou Pei ,  Theodore S. Fahlen

IPC分类号： H01J162

CPC分类号： H01J1/74 ,  H01J1/70 ,  H01J29/185 ,  H01J29/28 ,  H01J29/325 ,  H01J29/58

摘要： A light-emitting device (52) suitable for a flat-panel cathode-ray tube display contains a light-emissive region (66) formed over a plate (64). The light-emissive region contains a plurality of light-emissive particles (72). Part of the outer surface of each light-emissive particle is conformally covered with a coating (74) that provides light reflection or/and gettering.

摘要翻译： 适合于平板阴极射线管显示器的发光装置（52）包含形成在板（64）上的发光区域（66）。 发光区域包含多个发光颗粒（72）。 每个发光颗粒的外表面的一部分共形地覆盖有提供光反射和/或吸气的涂层（74）。

公开(公告)号：US06767784B2

公开(公告)日：2004-07-27

申请号：US09740174

申请日：2000-12-18

申请人： John D. Porter ,  William N. Thompson

发明人： John D. Porter ,  William N. Thompson

IPC分类号： H01L218234

CPC分类号： H01L27/1104 ,  G11C11/412

摘要： An SRAM memory cell is provided having a pair of cross-coupled CMOS inverters. The sources of the pull-up transistors forming each of the CMOS inverters are coupled to VCC through parasitic resistance of the substrate in which each is formed. The source of the p-type pull-up transistor is therefore always at a potential less than or equal to the potential of the N-well such that the emitter-base junction of the parasitic PNP transistor cannot become forward biased and latch-up cannot occur.

摘要翻译： 提供具有一对交叉耦合CMOS反相器的SRAM存储单元。 形成每个CMOS反相器的上拉晶体管的源极通过其中形成各自的衬底的寄生电阻耦合到VCC。 因此，p型上拉晶体管的源极总是处于小于或等于N阱的电位的电位，使得寄生PNP晶体管的发射极 - 基极结不能变为正向偏置，并且闭锁不能 发生。

公开(公告)号：US06642588B1

公开(公告)日：2003-11-04

申请号：US09620055

申请日：2000-07-20

申请人： John D. Porter ,  William N. Thompson

发明人： John D. Porter ,  William N. Thompson

IPC分类号： H01L2976

CPC分类号： H01L27/1104 ,  G11C11/412

摘要： An SRAM memory cell is provided having a pair of cross-coupled CMOS inverters. The sources of the pull-up transistors forming each of the CMOS inverters are coupled to VCC through parasitic resistance of the substrate in which each is formed. The source of the p-type pull-up transistor is therefore always at a potential less than or equal to the potential of the N-well such that the emitter-base junction of the parasitic PNP transistor cannot become forward biased and latch-up cannot occur.

公开(公告)号：US06556095B2

公开(公告)日：2003-04-29

申请号：US09929648

申请日：2001-08-14

申请人： William N. Thompson ,  John D. Porter ,  Larren Gene Weber

发明人： William N. Thompson ,  John D. Porter ,  Larren Gene Weber

IPC分类号： H03H1130

CPC分类号： G11C7/1051 ,  G11C7/1069 ,  H03H7/40 ,  H03H11/245 ,  H03H11/28 ,  H03H17/0263

摘要： A method of finding an unknown value from within a range of values is disclosed that divides the range into weighted subranges and then, beginning with an arbitrary search value within the range, performs a number of simple comparisons to determine the value for each subrange that will result in a match with the target value. This method can also detect those cases where the target value lies outside the range. In one embodiment, the method of finding an unknown value within a range of values is applied to impedance matching. In this embodiment, the output impedance of a pin on an integrated circuit is automatically matched to the impedance of the load connected to it. The output driver has a controllable impedance that can be adjusted within a specific range of impedances to match the external load impedance it is to drive.

公开(公告)号：US06545561B2

公开(公告)日：2003-04-08

申请号：US09929571

申请日：2001-08-14

申请人： William N. Thompson ,  John D. Porter ,  Larren Gene Weber

发明人： William N. Thompson ,  John D. Porter ,  Larren Gene Weber

IPC分类号： H03H1130

CPC分类号： G11C7/1051 ,  G11C7/1069 ,  H03H7/40 ,  H03H11/245 ,  H03H11/28 ,  H03H17/0263

摘要： A method of finding an unknown value from within a range of values is disclosed that divides the range into weighted subranges and then, beginning with an arbitrary search value within the range, performs a number of simple comparisons to determine the value for each subrange that will result in a match with the target value. This method can also detect those cases where the target value lies outside the range. In one embodiment, the method of finding an unknown value within a range of values is applied to impedance matching. In this embodiment, the output impedance of a pin on an integrated circuit is automatically matched to the impedance of the load connected to it. The output driver has a controllable impedance that can be adjusted within a specific range of impedances to match the external load impedance it is to drive.

公开(公告)号：US06476640B2

公开(公告)日：2002-11-05

申请号：US09850682

申请日：2001-05-07

申请人： John D. Porter ,  Larren G. Weber ,  William N. Thompson

发明人： John D. Porter ,  Larren G. Weber ,  William N. Thompson

IPC分类号： H03K1716

CPC分类号： H03K5/023 ,  H03K5/12 ,  H03K5/1252

摘要： A buffer having first and second input terminals and an output terminal. The buffer also includes a fast edge driver having an input terminal and an output terminal, with the input terminal connected to the first input terminal of the buffer, and the output terminal connected to the output terminal of the buffer. A shielding circuit is provided having an input terminal and an output terminal, with the input terminal connected to the second input terminal of the buffer. The buffer further includes a recovery circuit having an input terminal and an output terminal, with the input terminal connected to the output terminal of the shielding circuit, and the output terminal connected to the output terminal of the buffer.

摘要翻译： 具有第一和第二输入端子和输出端子的缓冲器。 缓冲器还包括具有输入端和输出端的快速边沿驱动器，输入端连接到缓冲器的第一输入端，输出端连接到缓冲器的输出端。 提供具有输入端子和输出端子的屏蔽电路，输入端子连接到缓冲器的第二输入端子。 该缓冲器还包括具有输入端和输出端的恢复电路，输入端连接到屏蔽电路的输出端，输出端连接到缓冲器的输出端。

公开(公告)号：US06469591B2

公开(公告)日：2002-10-22

申请号：US09888725

申请日：2001-06-25

申请人： William N. Thompson ,  John D. Porter ,  Larren Gene Weber

发明人： William N. Thompson ,  John D. Porter ,  Larren Gene Weber

IPC分类号： H03H1130

CPC分类号： G11C7/1051 ,  G11C7/1069 ,  H03H7/40 ,  H03H11/245 ,  H03H11/28 ,  H03H17/0263

摘要： A method of finding an unknown value from within a range of values is disclosed that divides the range into weighted subranges and then, beginning with an arbitrary search value within the range, performs a number of simple comparisons to determine the value for each subrange that will result in a match with the target value. This method can also detect those cases where the target value lies outside the range. In one embodiment, the method of finding an unknown value within a range of values is applied to impedance matching. In this embodiment, the output impedance of a pin on an integrated circuit is automatically matched to the impedance of the load connected to it. The output driver has a controllable impedance that can be adjusted within a specific range of impedances to match the external load impedance it is to drive.