-
公开(公告)号：US12190120B2
公开(公告)日：2025-01-07
申请号：US18312237
申请日：2023-05-04
Inventor： Asif Rashid Zargar , Roberto Colombo
IPC: G06F9/4401 , G06F21/64
Abstract: In embodiments, a reset management circuit executes reset, configuration, and software runtime phases when a processing system is switched on, where one or more microprocessors start at respective start addresses. During the configuration phase, a circuit reads a boot record from a non-volatile memory and stores it to registers. The circuit sequentially reads data records of configuration data from the non-volatile memory and generates a write request for each data record to store the data of the respective data record to a second circuit with associated address data indicated in the respective data record. The processing system processes the boot record and boot configuration data provided by the second circuits to selectively start a predetermined microprocessor at a default start address or at a start address indicated by the boot configuration data, or start one or more microprocessors at respective start addresses as indicated by the boot record.
-
公开(公告)号：US12061530B2
公开(公告)日：2024-08-13
申请号：US17655103
申请日：2022-03-16
Inventor： Roberto Colombo , Vivek Mohan Sharma
IPC: G06F11/22 , G06F11/07 , G06F11/273
CPC classification number: G06F11/2273 , G06F11/0772 , G06F11/079 , G06F11/2733
Abstract: A processing system includes a processing core including a microprocessor, a memory controller configured to read software instructions for execution by the processing core, a plurality of safety monitoring circuits configured to generate a plurality of error signals by monitoring operation of the processing core and the memory controller, a fault collection and error management circuit implemented as a hardware circuit, and a connectivity test circuit. The fault collection and error management circuit is configured to receive the plurality of error signals from the plurality of safety monitoring circuits and generate one or more reaction signals as a function of the plurality of error signals. The connectivity test circuit is configured to, during a diagnostic phase executed by the processing system after executing a reset phase and before executing a software runtime phase, test connectivity between the plurality of safety monitoring circuits and the fault collection and error management circuit.
-
公开(公告)号：US20230349969A1
公开(公告)日：2023-11-02
申请号：US18186549
申请日：2023-03-20
Inventor： Roberto Colombo , Vivek Mohan Sharma , Samiksha Agarwal
IPC: G01R31/317
CPC classification number: G01R31/31703 , G01R31/31722
Abstract: In an embodiment a processing system includes a test circuit configured to set an address value, an upper address limit and a lower address limit to a given reference bit sequence, verify whether the upper-limit comparison signal has a respective third logic level and/or whether the lower-limit comparison signal has the respective third logic level, assert an error signal in response to determining that the upper-limit comparison signal does not have the respective third logic level or the lower-limit comparison signal does not have the respective third logic level, repeat a certain operation for each of the N bits.
-
公开(公告)号：US20210382779A1
公开(公告)日：2021-12-09
申请号：US17406910
申请日：2021-08-19
Applicant: STMicroelectronics Application GMBH
Inventor： Roberto Colombo
Abstract: A processing system includes a plurality of circuits configured to generate a plurality of error signals. The processing system further includes a plurality of error pads and a fault collection circuit configured to receive the plurality of error signals and to generate a respective combined error signal for each of the plurality of error pads. The fault collection circuit includes a combinational logic circuit configured to generate the combined error signal by selectively routing the plurality of error signals to the plurality of error pads as a function of a set of configuring bits.
-
公开(公告)号：US11113136B2
公开(公告)日：2021-09-07
申请号：US16289405
申请日：2019-02-28
Applicant: STMicroelectronics Application GMBH
Inventor： Roberto Colombo
Abstract: A processing system includes a plurality of circuits configured to generate a plurality of error signals. The processing system further includes a plurality of error pads and a fault collection circuit configured to receive the plurality of error signals and to generate a respective combined error signal for each of the plurality of error pads. The fault collection circuit includes a combinational logic circuit configured to generate the combined error signal by selectively routing the plurality of error signals to the plurality of error pads as a function of a set of configuring bits.
-
Patent Agency Ranking
公开(公告)号：US10922015B2
公开(公告)日：2021-02-16
申请号：US16002534
申请日：2018-06-07
Applicant: STMicroelectronics Application GMBH
Inventor： Roberto Colombo
IPC: G06F3/06 , G06F15/78 , G06F15/177
Abstract: A processing system includes a processing unit; a non-volatile memory storing configuration data; and a configuration data client including a register, wherein the configuration data client is configured to receive the configuration data and store the configuration data in the register. The processing system further includes a hardware configuration circuit configured to read the configuration data from the non-volatile memory and transmit the configuration data, read from the non-volatile memory, to the configuration data client. The hardware configuration circuit may be configured to receive a command, including an access request, from the processing unit and selectively execute the access request.
-
公开(公告)号：US10855529B2
公开(公告)日：2020-12-01
申请号：US16679796
申请日：2019-11-11
Applicant: STMicroelectronics Application GmbH
Inventor： Roberto Colombo
IPC: H04L12/24 , H03K19/1776 , H04L29/06 , H04L29/08
Abstract: A hardware configuration circuit can sequentially read data packets from a non-volatile memory. For a first data packet, the circuit is configured to store the configuration data and the address included in the data packet in the register, select a target configuration data client circuit as a function of the address included in the first data packet, transmit a first data signal that includes the configuration data included in the first data packet to the target configuration data client circuit, receive a second data signal that includes configuration data stored in the target configuration data client circuit and the address associated with the target configuration data client circuit, and compare the configuration data and address received from the target configuration data client circuit with the configuration data and address stored in the register.
-
公开(公告)号：US12253562B2
公开(公告)日：2025-03-18
申请号：US18186624
申请日：2023-03-20
Inventor： Roberto Colombo , Vivek Mohan Sharma
IPC: G06F1/24 , G01R31/317 , G01R31/3185 , G06F11/14
Abstract: In an embodiment a processing system includes a reset circuit configured to receive a reset-request signal and one or more further reset-request signals, wherein the one or more further reset-request signals are provided by a processing core, one or more further circuits and/or a terminal of the processing system and to generate a combined reset-request signal by combining the reset-request signal and the one or more further reset-request signals, and a hardware test circuit including for each of the one or more further reset-request signals, a respective first combinational circuit configured to selectively assert the respective further reset-request signal, a second combinational logic circuit configured to selectively mask the combined reset-request signal, and a control circuit configured to repeat operations during a diagnostic phase.
-
公开(公告)号：US11762794B2
公开(公告)日：2023-09-19
申请号：US17747800
申请日：2022-05-18
Applicant: STMicroelectronics Application GMBH
Inventor： Rolf Nandlinger , Roberto Colombo
CPC classification number: G06F13/28 , G06F9/30105 , G06F9/3877 , G06F13/4282 , G06F21/602 , G06F21/72
Abstract: In an embodiment, a processing system comprises a microprocessor programmable via software instructions, a memory controller configured to be coupled to a memory, a communication system coupling the microprocessors to the memory controller, a cryptographic co-processor and a first communication interface. The processing system also comprises first and second configurable DMA channels. In a first configuration, the first DMA channel is configured to transfer data from the memory to the cryptographic co-processor, and the second DMA channel is configured to transfer the encrypted data via two loops from the cryptographic co-processor to the first communication interface. In a second configuration, the second DMA channel is configured to transfer received data via two loops from the first communication interface to the cryptographic co-processor, and the first DMA channel is configured to transfer the decrypted data from the cryptographic co-processor to the memory.
-
公开(公告)号：US11281514B2
公开(公告)日：2022-03-22
申请号：US16693103
申请日：2019-11-22
Applicant: STMicroelectronics Application GmbH
Inventor： Roberto Colombo
Abstract: A processing system includes a timer circuit and a processing circuit. The timer circuit is configured to generate a system time signal. The processing circuit is configured to receive the system time signal, detect whether the system time signal reaches or exceeds a given reference value, and start execution of a given processing operation in response to the detection. The timer circuit has associated an error code calculation circuit configured to compute a first set of error detection bits as a function of bits of the system time signal. The processing circuit has an associated error detection circuit configured to: compute a second set of error detection bits as a function of the bits of the system time signal received, compare the first set of error detection bits with the second set of error detection bits, and generate an error signal in response to the comparison.
-
-
-
-
-
-
-
-
-
Search Results
60
records
(took 0.026 seconds)
