公开(公告)号：US20150069399A1

公开(公告)日：2015-03-12

申请号：US14249329

申请日：2014-04-09

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Seung-Hwan Cho ,  Young Ki Shin ,  Dong Hwan Shim ,  Yoon Ho Khang ,  Hyun Jae Na

IPC: H01L29/786 ,  H01L29/66

CPC classification number: H01L29/7869 ,  H01L29/66969 ,  H01L29/78696

Abstract: A thin film transistor includes: a first semiconductor layer; a second semiconductor layer disposed on the first semiconductor layer; and a pair of source region and drain region formed by doping both sides of the first semiconductor layer and the second semiconductor layer with impurities, and the source region includes a first source layer on the same plane as the first semiconductor layer and a second source layer on the same plane as the second semiconductor layer, and the drain region includes a first drain layer on the same plane as the first semiconductor layer and a second drain layer on the same plane as the second semiconductor layer, and only one of the first semiconductor layer and the second semiconductor layer is a transistor channel layer.

Abstract translation: 薄膜晶体管包括：第一半导体层; 设置在所述第一半导体层上的第二半导体层; 以及通过用杂质掺杂第一半导体层和第二半导体层的两侧而形成的一对源区和漏区，源极区包括与第一半导体层在同一平面上的第一源极层和第二源极层 在与第二半导体层相同的平面上，漏区包括与第一半导体层相同的平面上的第一漏极层和与第二半导体层在同一平面上的第二漏极层，并且仅第一半导体 层，第二半导体层是晶体管沟道层。

公开(公告)号：US20140183522A1

公开(公告)日：2014-07-03

申请号：US14063774

申请日：2013-10-25

Applicant: Samsung Display Co., Ltd.

Inventor： Myoung Geun Cha ,  Yong Su Lee ,  Yoon Ho Khang ,  Hyun Jae Na ,  Se Hwan Yu ,  Jong Chan Lee ,  Dong Hwan Shim

IPC: H01L27/12 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L27/1222 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/78621 ,  H01L29/78633 ,  H01L29/7869

Abstract: A thin film transistor array panel including a substrate; a channel region disposed on the substrate and including oxide semiconductor disposed on the substrate; a source electrode and a drain electrode connected to the oxide semiconductor and facing each other at both sides, centered on the oxide semiconductor; an insulating layer disposed on the oxide semiconductor; and a gate electrode disposed on the insulating layer. The drain electrode includes a first drain region and a second drain region; the charge mobility of the first drain region is greater than that of the second drain region, the source electrode includes a first source region and a second source region, and the charge mobility of the first source region is greater than that of the second source region.

Abstract translation: 一种薄膜晶体管阵列面板，包括基板; 设置在所述基板上并且包括设置在所述基板上的氧化物半导体的沟道区; 连接到所述氧化物半导体并且以所述氧化物半导体为中心的两侧面对的源电极和漏电极; 设置在所述氧化物半导体上的绝缘层; 以及设置在所述绝缘层上的栅电极。 漏极包括第一漏区和第二漏区; 第一漏极区域的电荷迁移率大于第二漏极区域的电荷迁移率，源电极包括第一源极区域和第二源极区域，并且第一源极区域的电荷迁移率大于第二源极区域的电荷迁移率 。