Abstract:
Embodiments of the current disclosure to provide a display device which can reduce the number of intersections of scan lines and data lines. According to an embodiment of the disclosure, a display device comprises: a substrate; scan lines extending along a first direction; data lines extending along a second direction that intersect the first direction; a first switching element; a first pixel electrode connected to a first source electrode of the first switching element; a second switching element; and a second pixel electrode connected to a second source electrode of the second switching element. The first pixel electrode and the second pixel electrode are disposed along the second direction, and a first source electrode and a first drain electrode of the first switching element extend along the second direction in an area overlapping a first active layer of the first switching element.
Abstract:
A display device includes: a substrate; a first transistor and a second transistor disposed on the substrate; a first sub-pixel electrode electrically connected to a first drain electrode of the first transistor; a second sub-pixel electrode electrically connected to a second drain electrode of the second transistor; and color filter layers disposed between the first and second transistors and the first and second sub-pixel electrodes, the color filter layers including: a first color filter overlapping the first transistor and the first sub-pixel electrode, the first color filter representing a first color, and a first color filter pattern representing a second color different from the first color, the first color filter pattern overlapping the first transistor and the second transistor.
Abstract:
A thin film transistor array panel includes a first subpixel electrode and a second subpixel electrode electrically connected with a drain electrode through a first contact hole and a second contact hole, respectively. The first subpixel electrode and the second subpixel electrode include a plurality of vertical stems, a plurality of horizontal stems, and a plurality of branch electrodes. The first subpixel electrode is formed above a gate line and the second subpixel electrode is formed below a gate line. The thin film transistor array panel further includes a first protrusion formed in the plurality of vertical stems of the first subpixel electrode and the plurality of vertical stems of the second subpixel electrode.
Abstract:
Disclosed herein is a thin film transistor substrate, including: an insulating substrate having a dummy area and a display area; a signal line formed in the dummy area on the insulating substrate; a switching element positioned in the display area on the insulating substrate; a color filter layer positioned in the display area on the insulating substrate and exposing a portion of the switching element through at least one contact hole; and a dummy color filter layer positioned on the dummy area on the insulating substrate and exposing a portion of the signal line through at least one dummy contact hole, wherein the at least one dummy contact hole formed on the dummy color filter layer and the at least one contact hole formed on the color filter layer are formed on the same position in a plane view.
Abstract:
A substantially rectangular display panel includes a first edge extending in a first major axis direction of the rectangular shape and a second edge extending in a second major axis direction of the rectangular shape, the second direction being different from the first direction. The display panel includes: a plurality of gate lines extending in the first direction; and a gate lines driver including a plurality of main stages sequentially connected to each other and configured for outputting gate signals to the gate lines, where the plurality of stages further includes one or more dummy stages arranged in a row along the second edge and not connected to the plurality of gate lines, and where a layout arrangement of a plurality of thin film transistors included in the main stage is different from a corresponding layout arrangement of corresponding thin film transistors included in the at least one dummy stage.